Page 43 - Engineering Digital Design

14 CHAPTER 1 / INTRODUCTORY REMARKS AND GLOSSARY

EVM: entered variable K-map.
Excess 3 BCD (XS3) code: BCD plus three.
Excitation table: a state transition table relating the branching paths to the branching
condition values given in the state diagram for a flip-flop.
Exclusive OR: a two-variable function that is active if only one of the two variables is
active.
EXOP: XOR-sum-of-products.
Expansion of states: opposite of merging of states.
Extender: a circuit or gate that is designed to be connected to a digital device to increase
its fan-in capability — also called an expander.
Factoring law: the Boolean law that permits a variable to be factored out of two or more
p-terms that contain the variable in an SOP or XOR expression.
Fall time: the period of time it takes a voltage signal to change from 90% to 10% of its
high value.
Falling edge-triggered (FET): activation of a device on the falling edge of the triggering
(sampling) variable.
False carry rejection: the feature in an ALU where all carry-outs are disabled for all
nonarithmetic operations.
False data rejection (FDR): the feature of a code converter that indicates when unau-
thorized data has been issued to the converter.
Fan-in: the maximum number of inputs a gate may have.
Fan-out: the maximum number of equivalent gate inputs that a logic gate output can
drive.
FDR: false data rejection.
FDS diagram: fully documented state diagram.
FED: field emission display.
Feedback path: a signal path of a PS variable from the memory output to the NS input.
FET: falling edge-triggered. Also, field effect transistor.
Fetch: that part of an instruction cycle in which the instruction is brought from the memory
to the CPU.
FF: flip-flop.
Field programmable gate array (FPGA): a complex PLD that may contain a variety of
primitive devices such as discrete gates, MUXs and flip-flops.
Field programmable logic array (FPLA): one-time user programmable PL A.
FIFO: first-in-first-out memory register.
Fill bit: the bit of a combinational shifter that receives the fill logic value in a shifting
operation.
Finite state machine (FSM): a sequential machine that has a finite number of states in
which it can reside.
Flag: a hardware or software "marker" used to indicate the status of a machine.
Flip-flop (FF): a one-bit memory element that exhibits sequential behavior controlled
exclusively by a clock input.
Floating-gate NMOS: special NMOS used in erasable PROMs.
Floating point number (FPN) system: a binary number system expressed in two parts,
as a fraction and exponential, and that is used in computers to arithmetically manipulate
large numbers.
Flow chart: a chart that is made up of an interconnection of action and decision symbols
for the purpose of representing the sequential nature of something.