Page 48 - Engineering Digital Design

1.4 GLOSSARY OF TERMS, EXPRESSIONS, AND ABBREVIATIONS 19

Majority function: a function that becomes active when a majority of its variables become
active.
Majority gate: a logic gate that yields a majority function.
Mantissa: the fraction part of a floating point number.
Map: usually a Karnaugh map.
Map compression: a reduction in the order of a K-map.
N n
Map key: the order of K-map compression; hence, 2 ~ , where N is the number of
variables in the function to be mapped and n is the order of the K-map to be used.
Mapping algorithm: In FSM design, the procedure to obtain the NS functions by ANDing
the memory input logic value in the excitation table with the corresponding branching
condition in the state diagram for the FSM to be designed, and entering the result in the
appropriate cell of the NS K-map.
Master/slave (MS) flip-flop: a flip-flop characterized by a master (input) stage and a
slave (output) stage that are triggered by clock antiphase to each other.
Mask: to prevent information from passing a certain point in a given process.
Mask programmed: refers to the bit patterns produced in a PLD chip at the foundry.
Maxterm: a POS term that contains all the variables of the function.
Maxterm code: a code in which complemented variables are assigned logic 1 and un-
complemented variables are assigned logic 0 — the opposite of minterm code.
Mealy machine: an FSM that conforms to the Mealy model.
Mealy model: the general model for a sequential machine where the output state depends
on the input state as well as the present state.
Mealy output: a conditional output.
Medium-scale integrated circuits (MSI): 1C chips that contain 20 to 200 gates according
to one convention.
Memory: the ability of a digital device to store and retrieve binary words on command.
Memory element: a device for storing and retrieving one bit of information on command.
In asynchronous FSM terminology, a fictitious lumped path delay.
Merge: the concatenation of buses to form a larger bus.
Merging of states: in a state diagram, the act of combining states to produce fewer states.
Metal-oxide-semiconductor: the material constitution of an important logic family
(MOS) used in 1C construction.
Metastability: an unresolved state of an FSM that resides between a Set and a Reset
condition or that is logically unstable.
Metastable exit time: the time interval between entrance into and exit from the metastable
state.
MEV: Map entered variable.
Minimization: the process of reducing a logic function to its simplest form.
Minimum cover: the optimally reduced representation of a logic expression.
Minterm: a term in an SOP expression where all variables of the expression are repre-
sented in either complemented or uncomplemented form.
Minterm code: a logic variable code in which complemented variables are assigned
logic 0 while uncomplemented variables are assigned logic 1 —the opposite of maxterm
code.
Minuend: the operand from which the subtrahend is subtracted in a subtraction operation.
Mixed logic: the combined use of the positive and negative logic systems.