Page 51 - Engineering Digital Design

22 CHAPTER 1 / INTRODUCTORY REMARKS AND GLOSSARY

Ohm's law: voltage is linearly proportional to current, V = RI, where R is the constant
of proportionality called the resistance (in ohms).
One-hot code: a nonweighted code in which there exists only one 1 in each word of the
code.
One-hot design method: use of the one-hot code for synchronous and asynchronous
FSM design.
One-hot-plus-zero: one-hot code plus the all-zero state.
One's complement: a system of binary arithmetic in which a negative number is repre-
sented by complementing each bit of its positive equivalent.
Operand: a number or quantity that is to be operated on.
Operation table: a table that defines the functionality of a flip-flop or some other device.
Operator: a Boolean connective.
OPI: optional prime implicant.
Optional prime implicant (OPI): a prime implicant whose presence in a minimum
function produces alternative minimum cover.
OR: an operator requiring that the output of an OR gate be active if one or more of its
inputs are active.
OR-AND-Invert gate: a physical device, usually consisting of two OR gates and one
NAND gate, that performs the electrical equivalent of POS with an active low output.
Order: refers to the number of variables on the axes of a K-map.
OR function: a function that derives from the definition of OR.
ORG: output race glitch.
OR gate: a physical device that performs the electrical equivalent of the OR function.
OR laws: a set of Boolean identities based on the OR function.
OR plane: the ORing stage of a PLD.
Outbranching: branching from a state exclusive of the hold branching condition.
Output: a concluding signal issued by a digital device.
Output forming logic: the logic hardware in a sequential machine whose purpose it is to
generate the output signals.
Output holding register: a register, consisting of D flip-flops, that is used to filter out
output logic noise.
Output race glitch (ORG): an internally initiated function hazard that is produced by a
race condition in a sequential machine.
Overflow error: a false magnitude or sign that results from a left shift in a shifter when
there are insufficient word bit positions at the spill end.
Packing density: the practical limit to which switches of the same logic family can be
packed in an 1C chip.
PAL: programmable array logic (registered trademark of Advanced Micro Devices, Inc.).
PALU: programmable arithmetic and logic unit.
Parallel adder: a cascaded array of full adders where the carry-out of a given full adder
is the carry-in to the next most significant stage full adder.
Parallel load: the simultaneous loading of data inputs to devices such as registers and
counters.
Parity: related to the existence of an even or odd number of 1 's or O's in a binary word.
Parity bit: a bit appended to a binary word to detect, create, or remove even or odd parity.
Parity detector: a combinational logic device that will detect an even (or odd) number
of 1's (or O's) in a binary word.