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1.4 GLOSSARY OF TERMS, EXPRESSIONS, AND ABBREVIATIONS                 27


                  State: a unique set of binary values that characterize the logic status of a machine at some
                    point in time.
                  State adjacency set: any 2" set of logically adjacent states of an FSM.
                  State code assignment: unique set of code words that are assigned to an FSM to charac-
                    terize its logic status.
                  State diagram: the diagram or chart of an FSM that shows the state sequence, branching
                    conditions, and output information necessary to describe its sequential behavior.
                  State machine: a finite state machine (FSM). A sequential machine.
                  State identifier: any symbol (e.g., alphabetical) that is used to represent or identify a
                    state in a state diagram.
                  State table: tabular representation of a state diagram.
                  State transition table: (see excitation table).
                  State variable: any variable whose logic value contributes to the logic status of a machine
                    at any point in time. Any bit in the state code assignment of a state diagram.
                  Static hazard: an unwanted glitch in an otherwise steady-state signal that is produced by
                    an input change propagating along asymmetric path delays through inverters or gates.
                  Static-1 hazard: a glitch that occurs in an otherwise steady-state 1 output signal from SOP
                    logic due to a change in an input for which there are two asymmetric paths (delay-wise)
                    to the output.
                  Static-0 hazard: a glitch that occurs in an otherwise steady-state 0 output signal from POS
                    logic due to a change in an input for which there are two asymmetric paths (delay-wise)
                    to the output.
                  Static RAM: a nonvolatile form of RAM — does not need periodic refreshing to hold its
                    information.
                  Steering logic: logic based primarily on transmission gate switches.
                  S-term: a Boolean sum term — one containing only ORed literals.
                  Stretcher: an input conditioning device that catches a short input signal and stretches it.
                  STT: single transition time.
                  Stuck-at fault: an input to a logic gate that is permanently stuck at logic 0 or logic 1
                    because of a shorted connection, an open connection, or a connection to either ground
                    or a voltage supply.
                  Substrate: the supporting or foundation material in and on which a semiconductor device
                    is constructed.
                  Subtracter: a digital device that subtracts one binary word from another to give a differ-
                    ence and borrow.
                  Subtrahend: the operand being subtracted from the minuend in a subtraction operation.
                  Sum-of-products (SOP): the ORing of ANDed terms in a Boolean expression.
                  Sum rule: a rule in state diagram construction that requires that all possible branching
                    conditions be accounted for.
                  Switching speed: a device parameter that is related to its propagation delay time.
                  Synchronizer circuit: a logic circuit (usually a D flip-flop) that is used to synchronize
                    an input with respect to a clock signal.
                  Synchronous machine: a sequential machine that is clock driven.
                  Synchronous parallel load: parallel loading of a register or counter via a clock signal to
                    the flip-flops.
                  System level design: a design that includes controller and data path sections.
                  Tabular minimization: a minimization procedure that uses tables exclusively.
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