Page 44 - Engineering Digital Design

1.4 GLOSSARY OF TERMS, EXPRESSIONS, AND ABBREVIATIONS 15

Flow table: a tabular realization of a state diagram representing the sequential nature of
an FSM.
Fly state: a state (in a state diagram) whose only purpose is to remove a race condition.
A buffer state.
Forward bias: a voltage applied to a p-n junction diode in a direction as to cause the
diode to conduct (turn ON).
FPGA: field programmable gate array.
FPL A: field programmable logic array.
FPLS: field programmable logic sequencer.
Free set: variables of a function not used as the bond set in CRMT forms.
Frequency, f: the number of waveform cycles per unit time in Hz or s~'.
Frequency division: the reduction of frequency by a factor of f/n usually by means of
a binary counter, where n is the number of states in the counter.
FSM: finite state machine, either synchronous or asynchronous.
Full adder (FA): a combinational logic device that adds two binary bits to a carry-in bit
and issues a SUM bit and a carry-out bit.
Full subtracter (FS): a combinational logic device that subtracts a subtrahend bit and a
borrow-in bit from a minuend bit, and issues a difference bit and a borrow-out bit.
Fully documented state diagram: a state diagram that specifies all input branching
conditions and output conditions in literal or mnemonic form, that satisfies the sum
rule and mutually exclusive requirement, and that has been given a proper state code
assignment.
Function: a Boolean expression representing a specific binary operation.
Functional partition: a diagram that gives the division of device responsibility in a digital
system.
Function generator: a combinational logic device that generates logic functions (usually
via a MUX).
Function hazard: a hazard that is produced when two or more coupled variables change
in near proximity to each other.
Fundamental mode: the operational condition for an asynchronous FSM in which no
input change is permitted to occur until the FSM has stabilized following any previous
input change.
Fusible link: an element in a PLD memory bit location that can be "blown" to store a
logic 1 or logic 0 depending on how the PLD is designed.
Gain element: a device, such as a buffer, used to boost a signal.
GAL: general array logic.
Gate: a physical device (circuit) that performs the electrical equivalent of a logic function.
Also, one of three terminals of a MOSFET.
Gated basic cell: a basic cell that responds to its S and R input commands only on the
triggering edge of a gate or clock signal.
Gate/input tally: the gate and input count associated with a given logic expression — the
gate tally may or may not include inverters, but the input count must include both external
and internal inputs.
Gate-minimum logic: logic requiring a minimum number of gates; may include XOR
and EQV gates in addition to two-level logic.
Gate path delay: the interval of time required for the output of a gate to respond to an
input signal change.
Glitch: an unwanted transient in an otherwise steady-state signal.