Page 521 - Engineering Digital Design

CHAPTER 11

Synchronous FSM Design

Considerations and Applications

11.1 INTRODUCTION

A number of design considerations and problem areas were purposely avoided in the pre-
vious chapter. This was done to focus attention on the basic concepts of design and anal-
ysis. These design considerations and problem areas include logic noise in the output
signals; problems associated with asynchronous inputs, metastability, and clock distribu-
tion; and the initialization and reset of the FSM. It is the purpose of this chapter to discuss
these and other subject areas in sufficient detail so as to develop good, reliable design
practices.

11.2 DETECTION AND ELIMINATION OF OUTPUT RACE GLITCHES
Improper design of an FSM can lead to the presence of logic noise in output signals, and
this noise can cause the erroneous triggering of a next stage switching device to which the
FSM is attached. So it may be important that FSMs be designed to issue signals free of
unwanted logic transients (noise) called glitches.
There are two main sources of output logic noise in an FSM:

• Glitches produced by state variable race conditions
• Glitches produced by static hazards in the output logic

In this and the following section, both types of logic noise will be considered, with emphasis
on their removal by proper design methods.
A glitch that occurs as a result of two or more state variable changes during a state-
to-state transition is called an output race glitch or simply ORG. Thus, an ORG may be
regarded as an internally initiated function hazard (see Section 9.4), since two or more state
variables try to change simultaneously but cannot. A glitch is an unwanted transient in an
otherwise steady state signal and may appear as either a logic 0-1-0 (positive glitch) or as

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