Page 178 - Hardware Implementation of Finite-Field Arithmetic
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Slices Total time Cycles Period RAM Mult 5,292 147 36 1 39 2,272 2,072 37 56 – 37 2,001 190,050 7,602 25 1 34 1,594 79,838 4,202 19 1 35 1,754 5,875 235 25 1 34 1,609 2,527 133 19 1 35 1,894
LUTs 3,923 3,235 2,607 2,794 2,873 3,268
FFs 871 623 562 672 603 715 Cost and Delay of Dividers over GF (239 17 )
Pseudo Euclidean Binary Reduction to multiplications (MSE) Reduction to multiplications (LSE) Optimal extension field (MSE) Optimal extension field (LSE) TABLE 6.1
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