Page 173 - Hardware Implementation of Finite-Field Arithmetic

156 Cha pte r S i x

file reduction_to_multiplications.vhd is available at www.arithmetic-
circuits.org. The entity declaration is

entity reduction_to_multiplications is
port(
g, h: in polynomial;
clk, reset, start: in std_logic;
z: out polynomial;
done: out std_logic
);
end reduction_to_multiplications;

The VHDL architecture corresponding to the circuit of Fig. 6.3
follows:
with sel_mult select mult_in2 <=
e when “00”, h when “01”, g when others;
a_mod_f_multiplier: LSE_first_mod_f_mult port map
(e, mult_in2, clk, reset, start_mult, mult_out1,
mult_done);
with sel_e select next_ea <=
mult_out1 when ‘0’, mult_out2 when others;
an_inverter: mod_239_inverter port map(clk, a0, inv_a0);
mod_p_multipliers: for i in 0 to m-1 generate
a_mod_p_multiplier:
mod_239_multiplier port map(e(i), inv_a0,
mult_out2(i));
end generate;
register_e: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then e <= one_poly;
elsif ce_e = ‘1’ then e <= next_ea;
end if;
end if;
end process;
z <= e;
register_a: process(clk)
begin
if clk’event and clk = ‘1’ then
if ce_a = ‘1’ then a0 <= next_ea(0); end if;
end if;
end process;
The complete model additionally includes an s-state counter, a
shift register initially storing r − 1, and a control unit.

6.4 Optimal Extension Fields
A particularly interesting case is when f is a binomial and p a multiple
of m plus 1, that is,
m
f(x) = x – c and p mod m = 1 (6.28)
in which case Z [x]/f(x) is an optimal extension field (OEF).
p