Page 177 - Hardware Implementation of Finite-Field Arithmetic

160 Cha pte r S i x

has been generated. The complete VHDL file oef.vhd is available at
www.arithmetic-circuits.org. The entity declaration is

entity oef is
port(
g, h: in polynomial;
clk, reset, start: in std_logic;
z: out polynomial;
done: out std_logic
);
end oef;

The VHDL architecture corresponding to the circuit of Fig. 6.4
follows:

main_iteration: for j in 1 to m-1 generate
with sel_f select f_coef(j) <=
f1(j) when “00”, f2(j) when “01”, f4(j) when “10”,
f8(j) when others;
with sel_e select op1(j) <= a(j) when ‘0’,
e(j) when others;
with sel_e select op2(j) <= f_coef(j) when ‘0’,
inv_a0 when others;
mod_239_multipliers: mod_239_multiplier
port map(op1(j), op2(j), next_e(j));
end generate;
mod_239_multiplier2: mod_239_multiplier
port map(e(0), inv_a0, mult_out);
with sel_e select next_e(0) <= a(0) when ‘0’, mult_out
when others;
with sel_a select ahg <= a when “00”, h when “01”, g when
others;
mod_f_multiplier1: LSE_first_mod_f_mult
port map(e, ahg, clk, reset, start_mult, next_a,
mult_done);
z <= next_a;
inverter: mod_239_inverter port map(clk, a(0), inv_a0);
register_e: process(clk)
begin
if clk’event and clk = ‘1’ then
if ce_e = ‘1’ then e <= next_e; end if;
end if;
end process;
register_a: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then a <= h;
elsif ce_a = ‘1’ then a <= next_a;
end if;
end if;
end process;
The complete model additionally includes a control unit.