Page 238 - Hardware Implementation of Finite-Field Arithmetic

218 Cha pte r Se v e n

for i in 0 .. k loop
d(k) := m2xor(d(k),m2and(a(k-i),b(i)));
end loop;
for i in k+2 .. m-1 loop
d(k) := m2xor(d(k),m2and(a(m-1-(i-k-2)),b(i)));
end loop;
end loop;
for i in 1 .. m-1 loop
e := m2xor(e,m2and(a(m-1-(i-1)),b(i)));
end loop;
for i in 0 .. m-1 loop
c(i) := m2xor(e,d(i));
end loop;

An executable Ada file mastrovito_multiplication_AOP.adb,
including Algorithm 7.24, is available at www.arithmetic-circuits.org.
The VHDL model mastrovito_AOP_multiplication.vhd that implements
the algorithm has been generated. The entity declaration is

entity mastrovito_AOP_multiplication is
generic(M : natural := 8);
port (
a, b: in std_logic_vector(M-1 downto 0);
c: out std_logic_vector(M-1 downto 0)
);
end mastrovito_AOP_multiplication;

The VHDL architecture is the following:

d1: for k in 0 to m-1 generate
d2: process(d, a, b) variable aux: std_logic;
begin
aux := ‘0’;
for i in 0 to k loop aux := aux xor (a(k-i) and b(i));
end loop;
for i in k+2 to m-1 loop aux := aux xor (a(m-i+k+1))
and b(i)); end loop;
d(k) <= aux;
end process;
end generate;
e1: process(a, b) variable aux: std_logic;
begin
aux := (a(m-1) and b(1));
for i in 2 to m-1 loop aux := aux xor (a(m-i) and
b(i)); end loop;
e <= aux;
end process;
c1: for i in 0 to m-1 generate c(i) <= e xor d(i);
end generate;