Page 253 - Hardware Implementation of Finite-Field Arithmetic
P. 253

m
                             Operations over  GF (2 )—Polynomial Bases      233

                                                                       m
               [PL07] S. Peter and P. Langendörfer. “An Efficient Polynomial Multiplier in GF(2 )
                  and Its Application to ECC Designs.” Design, Automation and Test in Europe, pp.
                  1253–1258, 2007.
               [RH04]  A. Reyhani-Masoleh and  A. Hasan. “Low Complexity Bit Parallel
                  Architectures for Polynomial Basis Multiplication over  GF(2 ).”  IEEE
                                                                 m
                  Transactions on Computers, vol. 53, no. 8, pp. 945–959, August 2004.
               [RK03] F. Rodríguez-Henríquez, and Ç. K. Koç. “Parallel Multipliers Based on
                  Special Irreducible Pentanomials.” IEEE Transactions on Computers, vol. 52,
                  no. 12, pp. 1535–1542, December 2003.
               [RMSC06] F. Rodríguez-Henríquez, G. Morales-Luna, N. Saqib, and N. Cruz-Cortés.
                  “Parallel Itoh-Tsujii Multiplicative Inversion Algorithm for a Special Class of
                  Trinomials.” Cryptology ePrint Archive, Report 2006/035, 2006. http://eprint.
                  iacer.org/.
               [RSDK06] F. Rodríguez-Henríquez, N. Saqib,  A. Díaz-Pérez, and Ç. K. Koç.
                  Cryptographic Algorithms on Reconfigurable Hardware. Springer, New York, 2006.
               [SOOS95] R. Schroeppel, H. Orman, S. O’Malley, and O. Spatscheck. “Fast Key
                  Exchange with Elliptic Curve Systems,” Advances in Cryptology – Crypto’95,
                  LNCS 963, pp. 43–56, 1995.
               [Ser98] G. Seroussi. “Table of Low-Weight Binary Irreducible Polynomials.” HP
                  Labs Technical Report HPL-98–135, August 1998.
               [SK99] B. Sunar and Ç. K. Koç. “Mastrovito Multiplier for All Trinomials.” IEEE
                  Transactions on Computers, vol. 48, no. 5, pp. 522–527, May 1999.
               [SSTP88] P. A. Scott, S. J. Simmons, S. E. Tavares, and L. E. Peppard. “Architectures
                                     m
                  for Exponentiation in GF(2 ).” IEEE Journal on Selected Areas in Communications,
                  vol. 6, no. 3, pp. 578–586, April 1988.
               [Wan94] C.-L. Wang. “Bit-Level Systolic Array for Fast Exponentiation in GF(2 ).”
                                                                      m
                  IEEE Transactions on Computers, vol. 43, no. 7, pp. 838–841, July 1994.
               [Wu02] H. Wu. “Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial
                  Basis.” IEEE Transactions on Computers, vol. 51, no. 7, pp. 750–758, July 2002.
               [ZP01] T. Zhang and K. K. Parhi. “Systematic Design of Original and Modified
                  Mastrovito Multipliers for General Irreducible Polynomials.” IEEE Transactions
                  on Computers, vol. 50, no. 7, pp. 734–749, July 2001.
   248   249   250   251   252   253   254   255   256   257   258