Page 248 - Hardware Implementation of Finite-Field Arithmetic

228 Cha pte r Se v e n

7.7.9 Montgomery Squarer
The circuits were generated for specific polynomials and results for
fully combinationals and sequential circuits are shown in Tables 7.11
and 7.12, respectively.

m LUTs Slices Total time
8 6 3 3
16 16 8 3
32 67 35 6
64 193 99 8
128 418 214 25
163 267 147 20
233 117 74 7

TABLE 7.11 Cost and Delay of
Combinational Montgomery Squarer

m FFs LUTs Slices Period Cycles Total time
8 23 24 14 3.1 8 25
16 41 44 25 3.2 16 52
32 73 79 41 3.4 32 109
64 141 147 80 3.4 64 218
128 274 271 147 3.9 128 500
163 361 341 199 4.3 163 701
233 542 484 309 4.4 233 1,025

TABLE 7.12 Cost and Delay of Sequential Montgomery Squarer
7.7.10 Binary Exponentiation
The circuits were generated for specific polynomials. The circuits are
sequentials and the number of cycles depends on the amount of ones in
m
exponents. The worst case is when exponent e = 2 − 1 (i.e., all ones). The
cost and delay of binary exponentiation is shown in Table 7.13.

Average Worst
m FFs LUTs Slices Period time (μs) time (μs)
8 68 82 48 4.0 0.22 0.35
163 1,042 1,124 614 5.0 69 135
233 1,539 1,477 865 5.0 140 275

TABLE 7.13 Cost and Delay of Binary Exponentiation