Page 246 - Hardware Implementation of Finite-Field Arithmetic

226 Cha pte r Se v e n

m G FFs LUTs Slices Period Cycles Total time
163 1 509 511 271 5.0 163 815
163 2 527 676 369 4.5 82 369
163 4 531 849 463 4.8 41 197
163 6 538 1,017 555 4.8 28 134
163 8 555 1,356 745 5.0 21 105
163 11 546 1,843 965 5.2 15 78
163 13 515 1,884 975 5.7 13 74
163 15 528 2,215 1,161 5.8 11 64
163 33 560 4,449 2,304 7.5 5 37
163 55 589 6,956 3,588 9.7 3 29

G is the number of bits computed per clock cycle.
TABLE 7.5 Cost and Delay of Interleaved Advanced Multipliers and
7
3
6
f(x) = x 163 + x + x + x + 1
m G FFs LUTs Slices Period Cycles Total time
233 1 763 723 417 6.4 223 1,427
233 2 769 957 541 5.6 112 627
233 4 794 1,192 689 5.5 56 308
233 8 780 1,919 1,045 5.7 28 160
233 15 880 3,112 1,736 5.9 15 88
233 16 879 3,130 1,743 5.9 14 83
233 32 932 6,213 3,346 7.5 7 52
233 56 1,321 10,112 5,718 11.5 4 46

G is the number of bits computed per clock cycle.
TABLE 7.6 Cost and Delay of Interleaved Advanced Multipliers and f(x) = x 233 + x + 1
74

m LUTs Slices Total time
8 61 31 10
16 243 122 15
32 997 500 32
64 4,045 2,028 74
128 16,270 8,508 165
163 ∞
233 ∞
∞ means that the circuit does not fit within the device.
TABLE 7.7 Cost and Delay of Combinational
Montgomery Multiplier