Page 245 - Hardware Implementation of Finite-Field Arithmetic

m
Operations over GF (2 )—Polynomial Bases 225

m LUTs Slices Total time
8 59 30 4
16 255 128 9
32 1,068 537 14
64 4,466 2,242 22
128 ∞
163 ∞
233 ∞

∞ means that the circuit does not fit within the device.
TABLE 7.3 Cost and Delay of Mastrovito Multipliers
7.7.4 Mastrovito Multipliers, Second Version
The circuits were generated for specific polynomials and are fully
combinational (see Table 7.4).

m LUTs Slices Total time
8 53 28 3
16 222 112 8
32 934 473 13
64 3,728 1,877 18
128 14,249 14,249 30
163 22,347 15,201 36
233 ∞

∞ means that the circuit does not fit within the device.
TABLE 7.4 Cost and Delay for Second Version of
Mastrovito Multipliers
7.7.5 Interleaved Multiplication, Advanced Version
The combinational circuits are area avaricious; on the other hand
sequential circuits computing one bit of result at each cycle are slow. A
trade-off between area and speed can be used computing G bits per clock
cycle. The results of the cost and delay for the 163- and 233-bit NIST-
recommended polynomials are shown in Tables 7.5 and 7.6, respectively.

7.7.6 Montgomery Multipliers
The circuits were generated for specific polynomials and results for
fully combinational and sequential circuits are presented. The cost
and delay of several combinational and sequential Montogomery
multipliers are shown in Tables 7.7 and 7.8, respectively.