Page 250 - Hardware Implementation of Finite-Field Arithmetic

230 Cha pte r Se v e n

7.7.14 Modified Almost Inverse Algorithm (MAIA)
for Inversion
The circuits were generated for specific polynomials. The circuits are
sequential implementations (see Table 7.17).

m FFs LUTs Slices Period Cycles Total time
8 48 105 55 4.2 16 67
16 86 199 108 5.4 32 173
32 150 377 199 6.8 64 435
64 280 751 398 7.4 128 947
128 540 1,527 812 8.9 256 2,278
163 678 1,931 1,026 9.8 326 3,195
233 963 2,763 1,461 10.8 466 5,033
TABLE 7.17 Cost and Delay of MAIA for Inversion

7.7.15 Important Irreducible Polynomials
The circuits were generated for specific polynomials. Results are
presented for AOPs, trinomials, and class 1 pentanomials. The cir-
cuits are fully combinational. The cost and delay of several multipli-
ers using AOPs, trinomials, and class 1 pentanomials are shown in
Tables 7.18, 7.19, and 7.20, respectively.

m LUTs Slices Total time
10 46 24 4
60 3,055 2,101 9
130 14,154 8,590 15
196 32,121 20,455 ∞

∞ means that the circuit does not fit within the
device.
TABLE 7.18 Cost and Delay for AOPs

m LUTs Slices Total time Polynomial
9
9 67 44 5 x + x + 1
8
47
65
65 3,557 2,029 9 x + x + 1
83
129 13,978 8,266 ∞ x 129 + x + 1
167 23,370 14,362 ∞ x 167 + x 108 + 1
∞ means that the circuit does not fit within the device.
TABLE 7.19 Cost and Delay for Trinomials