Page 244 - Hardware Implementation of Finite-Field Arithmetic

224 Cha pte r Se v e n

available at www.arithmetic-circuits.org. The results for m = 163 and
m = 233 are using the NIST-recommended polynomials f(x) = x + x +
163
7
3
233
x + x + 1 and f(x) = x + x + 1.
74
6
7.7.1 Classic Multipliers
The circuits were generated for specific pol ynomials and are fully
combinational (see Table 7.1).
m LUTs Slices Total time
8 52 28 3
16 221 113 8
32 941 477 14
64 3,754 1,885 21
128 14,279 9,602 33
163 22,356 15,171 39
233 ∞
∞ means that the circuit does not fit within the
device.
TABLE 7.1 Cost and Delay of Classic Multipliers

7.7.2 Interleaved Multiplication
The circuits are for specific polynomials and are sequential
implementations that produce some results per cycle (see Table 7.2).

m FFs LUTs Slices Period Cycles Total time
8 32 36 20 3.1 8 25
32 108 115 62 3.5 32 112
64 208 211 114 3.9 64 250
128 405 405 216 4.8 128 614
163 527 511 287 5.0 163 815
233 765 725 420 5.0 233 1,165
TABLE 7.2 Cost and Delay of Interleaved Multipliers

7.7.3 Mastrovito Multipliers
The circuits were generated for specific polynomials and are fully
combinational. The cost and delay of several Mastrovito multipliers
are shown in Table 7.3.