Page 276 - Hardware Implementation of Finite-Field Arithmetic

256 Cha pte r Ei g h t

file NB_inversion.adb, including Algorithm 8.9, is available at
www.arithmetic-circuits.org.
An example of datapath corresponding to Algorithm 8.9 is shown
in Fig. 8.4. The minimum clock period is T NB_multiplier , and the total com-
putation time is about T ≈ mT . A VHDL model for the nor-
_
NB multiplier
mal basis inversion algorithm is given in the file NB_inversion.vhd,
which is available at www.arithmetic-circuits.org. The datapath cor-
responding to Algorithm 8.9 is shown in Fig. 8.4.
The entity declaration of the sequential implementation of the normal
basis inversion algorithm given in the VHDL file NB_inversion.vhd is

entity NB_inversion is
port (
a: in std_logic_vector(M-1 downto 0);
clk, reset, start: in std_logic;
done: out std_logic;
inv: out std_logic_vector(M-1 downto 0)
);
end NB_inversion;

The VHDL architecture corresponding to the circuit of Fig. 8.4
follows:

multiplier: NB_multiplier port map (a => bb, b => cc,
c => dd);
sq_register: process(clk)
begin
if reset = ‘1’ then bb <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if inic = ‘1’ then
bb <= a;
end if;
if shift_r = ‘1’ then
bb <= bb(M-2 downto 0) & bb(M-1);
end if;
end if;
end process sq_register;
register_C: process(inic, clk)
begin
if inic = ‘1’ or reset = ‘1’ then cc <= (others => ‘1’);
elsif clk’event and clk = ‘1’ then
if ce_c = ‘1’ then
cc <= dd;
else
cc <= cc;
end if;
end if;
end process register_C;
inv <= dd;
The complete model additionally includes a counter and a con-
trol unit.