Page 326 - Hardware Implementation of Finite-Field Arithmetic

306 Cha pte r T e n

A VHDL model has been generated. The complete VHDL file
K163_addition.vhd is available at www.arithmetic-circuits.org. The
entity declaration is
entity K163_addition is
port(
x1, y1, x2, y2: in std_logic_vector(m-1 downto 0);
clk, reset, start: in std_logic;
x3: inout std_logic_vector(m-1 downto 0);
y3: out std_logic_vector(m-1 downto 0);
done: out std_logic
);
end K163_addition;

The VHDL architecture corresponding to the circuit of Fig. 10.1 is
the following:

divider_inputs: for i in 0 to m-1 generate
div_in1(i) <= y1(i) xor y2(i);
div_in2(i) <= x1(i) xor x2(i);
end generate;
divider: binary_algorithm_polynomials port map(
g => div_in1, h => div_in2, clk => clk, reset => reset,
start => start_div, z => lambda, done => div_done
);
lambda_square_computation: classic_squarer port map(
a => lambda, c => lambda_square
);
x_output: for i in 1 to 162 generate
x3(i) <= lambda_square(i) xor lambda(i) xor
div_in2(i);
end generate;
x3(0) <= not(lambda_square(0) xor lambda(0) xor
div_in2(0));
multiplier_inputs: for i in 0 to 162 generate
mult_in2(i) <= x1(i) xor x3(i);
end generate;
multiplier: interleaved_mult port map(
a => lambda, b => mult_in2, clk => clk, reset => reset,
start => start_mult, z => mult_out, done => mult_done
);
y_output: for i in 0 to 162 generate
y3(i) <= mult_out(i) xor x3(i) xor y1(i);
end generate;

The complete model additionally includes a control unit.

10.5.3 Point Multiplication
As has been seen in Sec. 10.4.3.4, the branching conditions of Algo-
rithm 10.9 can be expressed in function of the least significant bits of
a and b: