Page 329 - Hardware Implementation of Finite-Field Arithmetic
P. 329

An Example of Application—Elliptic Curve Cryptography        309


               xor_gates: for i in 0 to m-1 generate
                  xxPxoryyP(i) <=xxP(i) xor yyP(i);
               end generate;
               with sel_1 select y1 <= yyP when ‘0’, xxPxoryyP when
               others;
               with sel_2 select next_yQ <= y3 when “00”, yyP when “01”,
               xxPxoryyP when others;
               with sel_2 select next_xQ <= x3 when “00”, xxP when
               others;
               first_component: K163_addition port map(
                  x1 => xxP, y1 => y1, x2 => xQ,  y2 => yQ, clk => clk,
                  reset => reset, start => start_addition, x3 => x3,
                  y3 => y3, done => addition_done
               );
               second_component: classic_squarer port map(
               a => xxP, c => square_xxP
               );
               third_component: classic_squarer port map(
               a => yyP, c => square_yyP
               );
               register_P: process(clk)
               begin
                  if clk’ event and clk = ‘1’ then
                     if load = ‘1’ then xxP <= xP; yyP <= yP;
                     elsif ce_P = ‘1’ then xxP <= square_xxP;
                     yyP <= square_yyP;
                     end if;
                  end if;
               end process;
               register_Q: process(clk)
               begin
                  if clk’ event and clk = ‘1’ then
                     if load = ‘1’ then Q_infinity <= ‘1’;
                     elsif ce_Q = ‘1’ then xQ <= next_xQ; yQ <= next_yQ;
                        Q_infinity <= ‘0’;
                     end if;
                  end if;
               end process;
               divide_by_2: for i in 0 to m-1 generate
                  a_div_2(i) <= a(i + 1);
               end generate;
               a_div_2(m) <= a(m);
               next_a <= (b(m-1)&b) + a_div_2 + carry;
               next_b <= zero - (a_div_2(m-1 downto 0) + carry);
               register_ab: process(clk)
               begin
                  if clk’ event and clk = ‘1’ then
                     if load = ‘1’ then a <= (‘0’&k); b <= zero;
                     elsif ce_ab = ‘1’ then a <= next_a; b <= next_b;
                     end if;
                  end if;
               end process;
               aEqual0 <= ‘1’ when a = 0 else ‘0’;
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