Page 333 - Hardware Implementation of Finite-Field Arithmetic
P. 333
APPENDIX A
192
64
p = 2 – 2 – 1
A.1 Hexadecimal Representation
48
192
64
16
p = 2 − 2 − 1 = 16 − 16 − 1
where
16 = [100 . . . 000 . . . 000]
48
16
48
16 − 1 = [FF . . . FFF . . . FFF]
16
p = (16 − 1) − 16 = [FF . . . FEF . . . FFF]
16
48
16
that is,
p = F, for i = 0 to 15 and i = 17 to 47 and p = E
i 16
A.2 mod p Reduction
A.2.1 Generic Sequential Circuit
In order to avoid the use of long-operand multipliers, nonrestoring or
SRT reducers should be used. Both types of reducers, for k = 192 and
n = 384, have been implemented. The packages storing the parameter
values are the following:
package nr_reducer_parameters is
constant N: natural := 384;
constant K: natural := 192;
--COUNTER_SIZE is the number of bits of N-K-1
constant COUNTER_SIZE: natural := 8;
end nr_reducer_parameters;
package srt_reducer_parameters is
constant N: natural := 384;
constant K: natural := 192;
--COUNTER_SIZE is the number of bits of N-K-1
constant COUNTER_SIZE: natural := 8;
end srt_reducer_parameters;
313
