Page 89 - Hardware Implementation of Finite-Field Arithmetic

72 Cha pte r T h ree

The min imum clock period of the circuit of Fig. 3.7 is determined
by the mod m adder computation time, that is, approximately kT
FA
[Eq. (3.2)]. The number of clock cycles is equal to 2k so that the total
computation time is

2
T ≈ 2k T (3.9)
FA
a rather bad result compared to Eq. (3.7).
A complete VHDL file dar_mod_multiplier.vhd is available at
www.arithmetic-circuits.org. The entity declaration is
entity dar_mod_multiplier is
port (
x, y: in std_logic_vector(K-1 downto 0);
clk, reset, start: in std_logic;
z: out std_logic_vector(K-1 downto 0);
done: out std_logic
);
end dar_mod_multiplier;
The VHDL architecture corresponding to the circuit of Fig. 3.7 is
the following:
with step_type select second_operand <= p when ‘0’, y when
others;
main_component: adder port map(p, second_operand, sum);
condition <= ce_p and (not(step_type) or x_i);
parallel_register: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then p <= (others => ‘0’);
elsif condition = ‘1’ then p <= sum;
end if;
end if;
end process parallel_register;
equal_zero <= ‘1’ when count = ZERO else ‘0’;
z <= p;
shift_register: process(clk)
begin
if clk’event and clk=’1’ then
if load = ‘1’ then int_x <= x;
elsif update = ‘1’ then
for i in k-1 downto 1 loop int_x(i) <= int_x(i-1);
end loop;
int_x(0) <= ‘0’;
end if;
end if;
end process shift_register;
x_i <= int_x(k-1);
The complete model additionally includes a k-state counter and a
control unit.