Page 85 - Hardware Implementation of Finite-Field Arithmetic

68 Cha pte r T h ree

entity modified_csa_multiplier is
port (
x, y: in std_logic_vector (K-1 downto 0);
clk, reset, start: in std_logic;
ps, pc, p: inout std_logic_vector (K-1 downto 0);
done: out std_logic
);
end modified_csa_multiplier;
The VHDL architecture corresponding to the circuit of Fig. 3.5 is
the following:

csa: for i in 0 to K-1 generate
next_s(i) <= ps(i) xor pc(i) xor y_by_xi(i);
next_c(i+1) <= (ps(i) and pc(i)) or (ps(i) and y_by_
xi(i))
or (pc(i) and y_by_xi(i)) ;
end generate;
and_gates: for i in 0 to K-1 generate
y_by_xi(i) <= y(i) and p(0);
end generate;
registers: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then
ps <= (others => ‘0’);
pc <= (others => ‘0’);
p <= x;
elsif update = ‘1’ then
ps <= ‘0’ & next_s(K-1 downto 1);
pc <= next_c(k)& next_c(K-1 downto 1);
p <=next_s(0) & p(K-1 downto 1);
end if;
end if;
end process;
The complete model additionally includes a k-state counter and a
control unit.
The structure of the complete carry-save mod m multiplier is
shown in Fig. 3.6. The first block is the modified_csa_multiplier entity
and the second one the srt_reducer entity (Sec. 2.1.3) with n = 2k, and
thus n − k = k. The circuit must be slightly modified: the initial value
of the register in Fig. 2.4 must be s = 000p (k − 1..0) and p(k − 1..0) =
s s
k
p (k − 1..0)2 + p(k − 1..0) and s = 000p (k − 1..0)00...0 = p (k − 1..0)2 , so
k
s c c c
that initially s + s = product [see Eq. (3.6)]. Within the VHDL architecture
s c
(Sec. 2.1.3) the process registers is modified accordingly, that is,
registers: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then ss <= (“000”&ps)&p; sc <= “000”&pc;
elsif update = ‘1’ then
...