Page 91 - Mechatronic Systems Modelling and Simulation with HDLs

80 4 MODELLING IN HARDWARE DESCRIPTION LANGUAGES

the operating point of the system is determined. There then follows a simulation
in the time, small-signal or noise range. If a model contains no quantities, then
the simulation is reduced to a pure logic simulation, which corresponds with the
predetermined simulation cycle in the VHDL 1076 standard, see [158] and [159].
If, on the other hand, a model does not include a digital signal, then the simulation
is exclusively analogue.
The simulation cycle of VHDL-AMS should be described based upon Algo-
rithm 4.1 below, which is formulated in pseudocode. The representation is some-
what simplified, for a complete version refer to [160].

Loop {
Call to the analogue solver;
Set current time T c to T n ;
If maximum time reached or no active
processes present then simulation end;
Bring digital signal to newest state;
Execute active, not delayed processes
up to the next synchronisation point (= WAIT);
Calculate next time point of digital activity T n ;
If T n =T c -- delta time interval
then proceed to the start of the loop;
Execute active, delayed processes
up to the next synchronisation point;
Calculate next time point of digital activity T n ;
}

Algorithm 4.1 Simplified simulation cycle of VHDL-AMS

The simulation cycle of VHDL-AMS includes the combined simulation of ana-
logue and digital processes and thus requires a corresponding linking of the digital
and analogue solution strategies. Initially the analogue solver is called up, which
in general calculates a solution up to time point T n. However, it may be necessary
for T n to be set back to T n (T n < T n), if the analogue world has produced a digital

event at time point T n . The current time T c is then set to T n or possibly to T n .If

the maximum representable time has now been reached by the time variables, or
there are no longer any active processes, the simulation is ended. Otherwise the
digital signals are set to the latest state and the active processes before the next
synchronisation point executed. However, the execution of some of these processes
is delayed. Then the next time of digital activity T n is calculated. If T n is equal to
T c then it is a time increment that elapses in zero time, i.e. a delta time increment.
In this case execution is restarted at the start of the loop. Otherwise the delayed
processes are executed and a new T n calculated. This completes the circle and
execution is recommenced at the start of the loop.