Page 146 - A Practical Guide from Design Planning to Manufacturing

Computer Architecture 119

by having simple instructions but also by having instructions of uniform
complexity. Transistor budgets also allowed for a larger number of reg-
isters. Making these visible to the programmer meant fewer memory
accesses were needed, therefore addressing modes were less important.
The continuing progress of Moore’s law means that today there are
new reasons to favor either the RISC or CISC approach. Although having
sufficient DRAM for instructions is rarely an issue today, the widening
gap between processor and main memory speed means that memory
bandwidth is a performance limiter. By having smaller code size, CISC
programs reduce the bandwidth to memory required to fetch instructions
and make better use of their instruction caches.
Processors’ transistor budgets now allow multiple parallel pipelines.
For CISC architectures, with variable length instructions, one instruction
must first be decoded before the starting byte of the next instruction can
be determined. RISC architectures, with fixed length instructions, allow
multiple instructions to be decoded easily in parallel.
Today most architects would agree RISC is the better choice, but
there hasn’t been a clear winner in the marketplace. All successful new
architectures created since the 1980s have used the RISC features
described in Table 4-18. Even Digital Equipment Corporation, the cre-
ator of the VAX architecture, which is considered the epitome of CISC,
eventually converted their computers to the Alpha architecture, which
was clearly a RISC design. However, the x86 architecture, which is
CISC, remains the most widely used desktop architecture. The per-
formance features of RISC have not yet been enough to overcome the
enormous value of binary compatibility.
In addition, the most recent x86 implementations have found ways to
use the same performance tricks as RISC processors. The Pentium 4 and
Athlon 64 use hardware to translate x86 instructions into simpler microin-
structions before execution. These microinstructions bare a striking
resemblance to RISC instructions. Converting complex instructions into
a stream of simple instructions in hardware, these processors are able
to take advantage of RISC features while maintaining compatibility.
They pay a price in die area and complexity to do this, but maintaining
backward compatibility makes it more than worth it.

TABLE 4-18 CISC versus RISC Architectures
RISC (SPARC, PA-RISC,
Feature CISC (VAX, x86) PowerPC)
Computation operands Memory operands allowed Register & immediate only
Instruction size Variable Fixed
Addressing modes Many Few
Architectural registers Few Many