Page 145 - A Practical Guide from Design Planning to Manufacturing

118 Chapter Four

CISC versus RISC
One question in modern computer architecture that made the little endian
versus big endian war seem like a minor skirmish was the debate of CISC
versus RISC. When RISC architectures were first being promoted in
the 1980s, many grand pronouncements were made on both sides; this
question of computer design sometimes took on the tones of a religious
war. Even at the time there wasn’t clear agreement on exactly what con-
stituted a RISC architecture. Some products were labeled RISC based
more on marketing strategy than their actual design, which caused Steven
Przybylski, one of pioneers of RISC architectures, to jokingly define
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RISC as “Any computer announced after 1985.” Using the concepts from
this chapter, we can list some basic differences between CISC and RISC
architectures.
The VAX and x86 architectures were created in the late 1970s when
program size was a large concern. DRAM memory was extremely expen-
sive and some programs were not practical because systems with enough
memory to run them were too expensive. Supporting memory and reg-
ister operands with many addressing modes allowed programs to use as
few total instructions as possible. In addition, variable length instruc-
tion formats allowed the most common instructions to be encoded in
fewer bits while using only longer formats for uncommon instructions.
By keeping the number of instructions and the average number of bytes
per instruction to a minimum, these architectures allowed the most func-
tionality using the least amount of instruction memory.
At the time transistor budgets did not allow for large numbers of reg-
isters. An architecture defining 32 registers or more would force any
processor implementing that architecture to dedicate an unreasonable
fraction of its total transistors to registers. In any case, serial execution
of instructions did not require a large number of registers.
As Moore’s law continued to drive DRAM and processor development
forward, RISC architectures made different choices to take advantage
of new possible implementations. As DRAM became more affordable,
minimizing code size became less important. Supporting fewer operand
types and allowing only fixed instruction sizes made RISC programs
much larger. However, it also made their implementation much simpler.
In the late 1980s, transistor budgets were sufficient to allow some of
the first pipelined processors. These began executing one instruction
before the previous was completed. To keep the pipeline full, it is impor-
tant that most instructions are executed in the same amount of time.
Every slow instruction causes faster instructions to pile up behind them
in the pipeline. RISC architectures allowed efficient execution not just

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ibid., Appendix C.