Page 371 - A Practical Guide from Design Planning to Manufacturing
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Silicon Debug and Test  341

        A bug’s life
        Bugs can be created at any point during the design. Imagine you are a
        logic designer on a processor design project. Tapeout is still 2 years away
        but the RTL model must be completed long before then. After a late
        night of coding and somewhere between the first and second coffee of the
        day, your fingers fumble as you type the name of a variable in your RTL
        code. By chance, the misspelled name is a valid variable, although a dif-
        ferent one than you intended. The RTL compiles successfully and a bug
        is created. This may seem like carelessness or merely bad luck, but when
        writing thousands of lines of code these types of mistakes inevitably
        happen. Any project that plans assuming its engineers will never make
        a mistake is surely doomed. Some common sources of logic bugs are: 6

          Goofs.  RTL typos and errors introduced when copying code from
          among similar functional areas.
          Microarchitectural flaws.  RTL faithfully reproduces the specified
          microarchitectural behavior, but this behavior itself does not produce
          the correct architectural result.
          Late changes. RTL code was correct but was changed late in design,
          creating a bug. The reason for a late change is often in order to fix a
          different bug.
          Corner cases. Common cases are implemented correctly but a combi-
          nation of different uncommon circumstances produces an incorrect result.
          Initialization. Most RTL simulations always start in the same state.
          Real silicon will have random values when powered up, which may
          cause bugs if not properly initialized.
          Pre-silicon validation attempts to detect and correct these bugs as
        soon as they are created, but the pre-silicon validation process is no more
        perfect than the engineers. Some bugs will lay undetected within the
        design until silicon testing. From the point of view of post-silicon vali-
        dation, a bug’s life begins the day it is detected and proceeds through the
        following steps:

        1. Detection
        2. Confirmation
        3. Work-around
        4. Root cause and fix
        5. Check for similar bugs


          6                     ®       ®
           Bentley, “Validating the Intel Pentium 4.”
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