Page 368 - A Practical Guide from Design Planning to Manufacturing

338 Chapter Eleven

of the total die area, the ability to tolerate a small number of defects in
the cache has a huge impact on die yield and therefore on die cost.
Modern processors could not be reliably tested without DFT circuits.
As the complexity of processors continues to grow steadily, more sophis-
ticated DFT circuits will be required. DFT is crucial not only for detect-
ing manufacturing defects but also for identifying design bugs during
post-silicon validation.

Post-Silicon Validation
The most important task as soon as first silicon chips are available is
looking for design flaws. Manufacturing defects will always affect some
percentage of the die, but until the design is correct, 100 percent of the
chips fabricated will be defective. Post-silicon validation tests real chips
for design bugs. A silicon bug is any unexpected (and usually undesired)
behavior detected in manufactured chips. There are five basic cate-
gories of silicon bugs:

1. Logic bug
2. Performance bug
3. Speedpath
4. Power bug
5. Circuit marginality

The most serious bugs are logic bugs: cases where the new design pro-
duces an incorrect result. The Pentium FDIV bug is probably the most
famous example of a silicon logic bug. In one version of the Intel Pentium
for some combinations of inputs, the result of a divide instruction was
incorrect. Looking for logic bugs is the first and primary focus of post-
silicon validation.
Designs with performance bugs produce the correct result but take
more time than expected to reach it. Imagine a design that, because of a
bug, predicts every branch as taken no matter what is its real behavior.
This prediction will be wrong a large percentage of the time, causing pro-
grams to execute very slowly, but they will eventually produce the correct
result. Validation must not only check the results of applications but also
that the number of cycles to generate the result matches expectations.
Speedpaths are circuit paths that limit the frequency of a processor.
They prevent the processor from producing the correct result at the
target clock frequency. Of course, some circuit paths on the die will
always be the slowest, but designers use pre-silicon timing simulations
to attempt to make the worst circuit paths in all parts of the die meet
the same target frequency. If a small number of paths are limited to a