Page 385 - A Practical Guide from Design Planning to Manufacturing

Silicon Debug and Test 355

Review Questions

1. Why do all designs find bugs post-silicon?
2. What are some common causes of logic bugs?
3. What is the difference between deadlock and livelock?
4. How does a stored-response tester work?
5. Describe five ways in which a design bug could be corrected.
6. Describe three types of post-silicon validation tests.
7. How are FIB edits used in silicon debug?
8. What types of silicon bugs are suitable for errata?
9. What is the purpose of burn-in testing?
10. What is the advantage of performing E-test and wafer probe testing?
11. [Discussion] What are the possible impacts of creating a processor
design without DFT circuits? Would it be possible to validate a
design using DFT circuits and then manufacture a version without
them? What would be the advantages to and problems with this
approach?
12. [Discussion] This text states that all microprocessors have errata.
Is this true for other complex products? In what markets besides
computers and under what circumstances are errata considered
acceptable? When are they not acceptable?
13. [Discussion] Of all the steps in microprocessor design which is most
impacted by the scaling of Moore’s law?

Bibliography

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Conference, Winchester, England: 2002.
Bentley, Bob. “High Level Validation of Next-Generation Microprocessors.” 7th IEE
International High-Level Design Validation and Test Workshop, Cannes, France: October
2002.
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Bentley, Bob. “Validating the Intel Pentium 4 Microprocessor.” Design Automation
Conference, Las Vegas, NV: 2001.
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Carbine, Adrian and Derek Feltham. “Pentium Pro Processor Design for Test and Debug.”
International Test Conference, Washington, DC: 1997.
Chandrakasan, Anantha et al. Design of High-Performance Microprocessor Circuits. New
York: Wiley-IEEE Press, 2001.
Chang, Jonathan et al. “A130-nm Triple-Vt 9-MB Third-Level On-Die Cache for the 1.7-GHz
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Itanium 2 Processor.” IEEE Journal of Solid State Circuits, vol. 40, 2005, pp. 195–203.
[Describes the redundancy used to improve yields with an extremely large cache.]
Dervisoglu, Bulent. “Design for Testability: It Is Time to Deliver It for Time-to-Market.”
International Test Conference, Atlantic City, NJ: 1999.