Page 390 - A Practical Guide from Design Planning to Manufacturing

360 Glossary

Built-in self test (BIST) Circuits added to an integrated circuit capable of
generating stimulus and comparing outputs of expected values in order to test
a circuit block.
Bulk wafer A silicon wafer cut from a crystal ingot.
Bumping The process of adding solder bumps to finished die on a wafer before
assembly into a flip-chip package.
Bumpless buildup layer (BBUL) packaging Packaging that uses the die itself
as one of the core layers of the package. Package interconnects are built around and
on top of the die, eliminating the need for die bumps and reducing package size.
Burn-in High-voltage and high-temperature stress testing designed to trigger
latent defects and avoid shipping parts that would fail early in their lifetime.
Byte A group of 8 bits.
C4 Controlled collapse chip connections.

Cache coherency Protocols used to handle data sharing among multiple
caches in a multiprocessor computer.
Cache hit When the memory address being searched for is currently held in
cache memory.
Cache memory High-speed memory that holds recently accessed data or
instructions in order to improve performance by reducing the average latency
of accesses to memory.
Cache miss When the memory address being searched for is not currently held
in cache memory.
Call instruction A computer instruction that redirects program execution to
a new instruction after pushing the current instruction address onto the stack
so that a return instruction will resume execution with the instruction imme-
diately after the call. This allows the same block of code to be executed from
many places and still return to the correct point in the program.
Canonical sum A function written as the logical sum of fundamental products
each of which is true for only one combination of inputs.
Capacity miss A cache miss that would not have occurred in a larger cache.
Capillary underfill (CUF) Epoxy that can flow in between the C4 bumps of a
die facedown on a package in order to hold the die in place under the stress
caused by heating during use.
Carrier mobility The ability of free charge carriers in a semiconductor to move
under the influence of an electric field. Higher mobility leads to higher currents
and higher switching speeds. In silicon, N-type carriers typically have twice the
mobility of P-type carriers, allowing NMOS transistors to produce the same cur-
rent as PMOS transistors of twice the width.
CBD Cell-based design.