Page 391 - A Practical Guide from Design Planning to Manufacturing

Glossary 361

Cell-based design (CBD) A partial automated design method for creating
layout by using a library of predesigned cells.
Ceramic dual in-line package (CERDIP) A ceramic package with rows of leads
on two sides.
Chemical mechanical planarization (CMP) A manufacturing process to create
a flat surface for the next processing step by spinning the wafer in an abrasive
slurry.
Chemical vapor deposition (CVD) Deposition of material through the chem-
ical reaction of gases.
Chip on board (COB) Attaching a bare integrated circuit die directly to a
printed circuit board. Also called direct chip attach (DCA).
Chip scale package (CSP) An integrated circuit package with area less than
1.5 times the die area.
Chipset A pair of chips responsible for communication between the processor
and other components on the motherboard. Typically one chip of the chipset is
responsible for communication with high-speed components and the other with
lower-speed components.
Circuit design The design step of changing logic (usually written into RTL)
into a transistor implementation.
Circuit marginality A design problem that only appears at certain combinations
of voltage, temperature, and frequency.
CISC Complex instruction set computing.
Cleanroom An integrated circuit fabrication facility where particles in the air
are carefully controlled to limit manufacturing defects. The class of cleanroom
is measured by the average number of particles above 0.5 µm in diameter per
cubic foot of air.
Clock jitter Variation in clock frequency, causing some clock cycles to be longer
or shorter than others.
Clock skew Variation in the arrival of a single clock edge at different points
on the die, causing some sequentials to receive the clock signal before others.
CMOS Complementary metal oxide semiconductor.
CMP Chemical mechanical planarization.
COB Chip on board.
Coefficient of thermal expansion (CTE) The rate at which a material expands
when heated. When assembling die into a package or packages onto a board it
is important to try and minimize differences in CTE in order to limit the mechan-
ical stress caused by heating.
Cold miss A cache miss caused by a memory address being accessed for the
first time.