Page 58 - A Practical Guide from Design Planning to Manufacturing

34 Chapter One

Key Concepts and Terms
Bipolar junction transistor (BJT) Metal oxide semiconductor field-effect
Channel length transistor (MOSFET)
Conduction and valence bands Moore’s law
Electrons and holes N-type, P-type
Gate oxide Polycrystalline silicon (Poly)
Integrated circuit (IC) Silicon on insulator (SOI)
Junction diode Threshold voltage
Lead design and compaction

Review Questions
1. What column elements are used as P-type or N-type dopants and why?
2. Describe the valence and conduction bands of a conductor, an insu-
lator, and a semiconductor.
3. How is a BJT different than a MOSFET?
4. Why is poly commonly used for MOSFET gates?
5. What are some of the trade-offs in choosing channel length, gate
oxide thickness, and threshold voltage?
6. How do microprocessor fabrication processes typically scale over time?
7. In addition to simple scaling what are other fabrication technologies
to improve transistor performance?
8. Why is Moore’s law so important to the semiconductor industry?
9. [Lab] Measure the current versus voltage of a junction diode. Is the
current in reverse bias always zero?
10. [Discussion] What are some of the limits to Moore’s law and ways
of addressing these limits? How long will Moore’s law continue?
How might electronics continue to evolve after Moore’s law?

Bibliography
“AMD and 90nm Manufacturing: Paving the Way for Tomorrow, Today.”
http://www.amd.com/us-en/Processors/ComputingSolutions.
Bakoglu, H., Circuits, Interconnections, and Packaging for VLSI, Reading, MA: Addison-
Wesley, 1990.
Bhandarkar, Dileep. “Billion Transistor Processor Chips in the Mainstream Enterprise
Platforms of the Future.” Ninth International Symposium on High Performance
Computer Architecture, Anaheim, CA: 2003.
Bohr, Mark et al. “A High Performance 0.25 µm Logic Technology Optimized for 1.8 V
Operation.” International Electronic Devices Meeting, San Francisco, CA: 1996, pp. 847–850.
[Describes Intel’s 250-nm process generation.]
Bohr, Mark. “Interconnect Scaling—The Real Limiter to High Performance ULSI.” Solid
State Technology, September 1996, pp. 105–111.