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        Bohr, Mark. “Silicon Trends and Limits for Advanced Microprocessors.” Communications
          of the ACM, March 1998, pp. 80–87.
        Ceruzzi, Paul. A History of Modern Computing. 2d ed., Cambridge, MA: The MIT Press, 2003.
        Chau, Robert. “Silicon Nano-Transistors and Breaking the 10nm Physical Gate Length
          Barrier.” 61st Device Research Conference, Salt Lake City, UT: June 2003.
        Chen, Gang et al. “Dynamic NBTI of p-MOS Transistors and Its Impact on MOSFET
          Scaling.” IEEE Electron Device Letters, San Francisco, CA: 2002.
        David, Ken. “Silicon Research at Intel.” Global Strategic Forum, Washington DC: March 2004.
        Dennard, Robert et al. “Design of Ion-Implanted MOSFETs with Very Small Dimensions.”
          IEEE Journal of Solid Static Circuits, 1974, pp. 256–268.
        Einstein, Marcus and James Franklin, “Computer Manufacturing Enters a New Era of
          Growth.” Monthly Labor Review, September 1986, pp. 9–16.
        Flatow, Ira et al. “Transistorized.” ScienCentral Inc. and Twin Cities Public Television, 1998,
          http://www.pbs.org/transistor/index.html. [Afun and extremely accessible public television
          special on the invention of the transistor. Based mainly on the book Crystal Fire.]
        Flynn, Michael and Patrick Hung, “Microprocessor Design Issues: Thoughts on the Road
          Ahead,” IEEE Computer Society, Los Alamitos, CA: 2005. [A great discussion of the
          impact of Moore’s law on design.]
        Ghani, Tahir. et al. “A 90nm High Volume Manufacturing Logic Technology Featuring
          Novel 45nm Gate Length Strained Silicon CMOS Transistors.” International Electronic
          Devices Meeting, Washington DC: 2003. [Describes Intel’s 90-nm process generation.]
        Ghani, Tahir. et al.  “100nm Gate Length High Performance/Low Power CMOS Transistor
          Structure.” International Electronic Devices Meeting, Washington DC: 1999, pp. 415–418.
          [Describes Intel’s 180nm process generation.]
        McFarland, Grant. “CMOS Technology Scaling and Its Impact on Cache Delay.” Stanford
          University PhD Dissertation, 1995. [My own PhD dissertation did a fair job of
          predicting the characteristics of the 90-nm process generation, which was reached 10
          years later.]
        Moore, Gordon. “Cramming More Components onto Integrated Circuits.” Electronics,
          April 1965, pp. 114–117. [The original paper showing Moore’s law. Predicts a doubling
          of the number of transistors on a die every year from 1959 to 1975. Moore’s 1975 paper
          revised this to a doubling every 18 months.]
        Moore, Gordon. “Progress in Digital Integrated Electronics.” International Electronic
          Devices Meeting, December 1975, pp. 11–13. [The second and most often quoted
          formulation of Moore’s law.]
        Moore, Gordon. “No Exponential is Forever... But We Can Delay Forever.” International
          Solid State Circuits Conference, San Francisco, CA: February 2003. [A great update on
          Moore’s law by the creator himself.]
        Muller, Richard and Theodore Kamins. Device Electronics for Integrated Circuits. 2d ed.,
          New York: John Wiley & Sons, 1986. Real, Mimi. A Revolution in Progress: A History of
          Intel to Date. Santa Clara, CA: Intel Corporation, 1984.
        Reid, T. R. The Chip, Random House Trade Paperbacks, 2001. [Tells the story of the
          invention of the integrated circuit by Jack Kilby and Bob Noyce.]
        Riordan, Michael and Lillian Hoddeson. Crystal Fire, New York: W. W. Norton & Company,
          1997. [Tells the story of the invention of the transistor.]
        Roberts, Bruce, Alain Harrus, and Robert Jackson. “Interconnect Metallization for Future
          Device Generations.” Solid State Technology, February 1995, pp. 69–78.
        Thompson, Scott et al. “A Logic Nanotechnology Featuring Strained-Silicon.” IEEE
          Electron Device Letters, April 2004, pp. 191–193. [A description of the strained silicon
          technique used in Intel’s 90-nm process generation.]
        Thompson, Scott et al. “MOS Scaling: Transistor Challenges for the 21st Century.” Intel
          Technology Journal, Q3 1998, pp. 1–19.
        Walden, Josh. “90nm and Beyond: Moore’s Law and More.” Intel Developer Forum, San
          Jose, CA: April 2003.
        Walker, Robert et al. “Silicon Genesis: An Oral History of Semiconductor Technology.”
          http://silicongenesis.stanford.edu. [An incredible collection of interviews with many of
          the founders of silicon valley including Gordon Moore, Ted Hoff, Fedrico Faggin, Jerry
          Sanders, and many others.]
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