Page 68 - A Practical Guide from Design Planning to Manufacturing

44 Chapter Two

common computer components. This is attractive because it requires less
physical space than a separate processor and chipset and packaging
costs are reduced. However, it makes the processor design dependent
upon the different bus standards it supports.
Supporting multiple standards requires duplicate hardware for each
standard built into the processor or supporting different versions of the
processor design. Because the microprocessor is much more expensive
to design, validate, and manufacture, it is often more efficient to place
these functions which depend upon constantly improving bus standards
on separate chips. As new bus standards become widely used, chipsets
are quickly developed to support them without affecting the design of
the microprocessor. For portable and handheld products where physi-
cal space is at a very high premium, it may be worth giving up the flex-
ibility of a separate chipset in order to reduce the number of chips on the
motherboard, but for desktop computers it seems likely that a separate
chipset is here to stay.

Processor Bus
The processor bus controls how the microprocessor communicates with
the outside world. It is sometimes called the Front-Side Bus (FSB).
Early Pentium III and Athlon processors had high-speed cache memory
chips built into the processor package. Communication with these chips
was through a back-side bus, making the connection to the outside world
the front-side bus. More recent processors incorporate their cache
memory directly into the processor die, but the term front-side bus
persists. Some recent processor bus standards are listed in Table 2-1.
The Athlon XP enables two data transfers per bus clock whereas the
Pentium 4 enables four. For both processors, the number in the name
of the bus standard refers to the number of millions of transfers per
second. Because both processors perform more than one transfer per

TABLE 2-1 Processor Bus Standards
Processor Transfers Max data
Processor Bus width bus clock Transfers per second bandwidth
bus (b) (MHz) per clock (MT/s) (MB/s)
Athlon XP FSB200 64 100 2 200 1600
Athlon XP FSB266 64 133 2 266 2133
Athlon XP FSB333 64 167 2 333 2667
Athlon XP FSB400 64 200 2 400 3200
Pentium 4 FSB400 64 100 4 400 3200
Pentium 4 FSB533 64 133 4 533 4267
Pentium 4 FSB800 64 200 4 800 6400