Page 406 - Offshore Electrical Engineering Manual

Fault Trees 393

The frequency of occurrence may either be a numerical value obtained from a
reliability data bank or a qualitative level assigned as follows:

Level A Frequent A high probability of occurrence during the time the
system is running
Level B Reasonably probable A moderate probability of occurrence during the time
the system is running
Level C Occasional An occasional probability of occurrence during the
time the system is running
Level D Remote An unlikely probability of occurrence during the time
the system is running
Level E Extremely unlikely A failure whose probability of occurrence is essen-
tially zero during the time the system is running

A diagonal line is drawn on the matrix and each failure mode effect which has
no existing compensating provision should be represented by a cross drawn on the
matrix. Failure effects appearing in the upper right-hand area of the graph have the
greatest criticality and hence the most urgent need for corrective action.

FAULT TREES
A fault tree is a graphical method of describing how faults in system components
relate to overall system failures. The rules for constructing a fault tree will, if rigidly
adhered to, lead to the creation of a graphical model of the system which will greatly
assist the system designer in ensuring that as many failure modes as possible are
remedied at the design stage.
A typical fault tree model is shown in Fig. 8.1.4. The diamond or circle shapes
represent basic events which are component failure modes.
Combination events, which are the logical result of a combination of basic events,
are represented by rectangles. The logic of the tree is shown by using mainly ‘AND’
and ‘OR’ gates.
The AND gate represents a situation where a combination event can only exist if
the basic events connected to it by the AND gate all exist simultaneously.
The OR gate represents the situation where a combination event can exist if one
or more of the basic events connected to it by the OR gate exist. Other logic devices
can be used to represent standby equipment, voting systems, etc., and in most cases,
normal Boolean algebra rules apply.

FAULT TREE CONSTRUCTION
As with all methods of reliability analysis, the system boundaries must be carefully
defined. A block diagram of the system should be drawn which shows all exter-
nal inputs, as these should be identified in the fault tree construction. This process
assists the analyst to understand the function of the system. An FMECA should be