Page 44 - Organic Electronics in Sensors and Biotechnology

Scaling Effects in Organic Transistors and Transistor-Based Chemical Sensors 21

1.1.5 Charge Transport in sub-10-nm Organic Transistors
Organic thin-film transistors have received great interest from the
scientific community due to their use in potentially low-cost, large-area
circuits. 10, 70 Characteristics of top contact organic thin-film transis-
tors have been reported for channel lengths down to 30 nm fabri-
71
cated with e-beam lithography. Recently several groups reported
their work on the performance of bottom contact organic thin-film
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transistors down to 50 nm and 30 nm channel lengths, also defined
72
by e-beam lithography. Compared to the expensive e-beam lithogra-
phy process, emerging techniques such as nanoimprint lithography
combined with dry etching process have captured the attention of
industry due to their potential as fast and inexpensive candidates to
fabricate nanoscale devices. There have been several reports for uti-
lizing these techniques to fabricate organic/polymeric transistors
75
with channel lengths of 500 nm and 70 nm. The transport mecha-
74
nisms would be different when the channel length of a transistor
shrinks to sub 10 nm, since tunneling effects become important at
these dimensions and it is also likely that charge transport between
source and drain takes place through a single grain. Charge injection
from the contact would play a very important role in such a small
geometry device as well. Indeed, a situation could exist in which the
local morphology of organic semiconductor in the vicinity of the
channel dominates the device behavior, leading to huge variations in
individual transistor responses. At the high longitudinal electric
fields present in devices with very small channel lengths, the carrier
velocity rather than mobility becomes important. This velocity may
saturate at high fields, leading to a reduction in the effective mobility
at high fields.
The field-effect transistors of channel length below 10 nm were
fabricated on a heavily doped silicon substrate serving as the gate
and a thermally grown SiO layer as the gate dielectric. The electrode
2
patterns were defined by e-beam lithography, metallization, and lift-
off process. Electrode patterns of channel lengths ranging from 40 nm
down to sub 10 nm were obtained. A pattern of a 5 nm channel with
side guards as close as 20 nm away is shown in Fig. 1.13a. Bottom-
contact devices were completed by subliming pentacene molecules,
resulting in pentacene layer with an average grain size of about 100 nm.
The dc electrical characteristics of the transistors were measured in
air at room temperature. After the measurements, all the devices were
examined by SEM. Figure 1.13b shows the post-measurement SEM
image of a bottom-contact pentacene transistor of 9 nm channel
length. By applying the same potential as the drain on the two side
guards, the true source-to-drain current (−I ) was observed as shown
ds
in Fig. 1.14a. The behavior of I exhibited reasonable gate modula-
ds
tion. Due to the thickness of the gate dielectric layer (100 nm SiO ),
2
the operating gate voltage (V , up to −30 V) in most cases is much
g