Page 138 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL ANALYSIS Ronald E. Best 87

TABLE 3.3 Summary of Parameters of the Mixed-Signal PLL, Phase Detector Type 3
(JK-Flipflop)

This dilemma can be fixed by using the so-called fastlock technique, which will be
discussed in Sec. 3.10.1.

Fastlock techniques
To achieve fastlock, the bandwidth of the PLL is made large when it has not yet locked. As
soon as lock is detected, the bandwidth is reduced to a smaller value. The fastlock technique
will be explained by the example of a PLL that uses a current output PFD. (Such an
application is found, for example, in the PLL frequency synthesizer chip type LMX 2470
54
manufactured by National Semiconductors. ) According to Eq. (3.23) for this type of PLL,
the natural frequency ω and damping factor ζ are given by
n