Page 168 - Phase-Locked Loops Design, Simulation, and Applications

PLL PERFORMANCE IN THE PRESENCE OF NOISE Ronald E. Best 103
■ The noise bandwidth B is a function of ω and ζ. For ζ = 0.7, B = 0.53 ω .
L n L n
■ The average time interval T between two unlocking events gets longer as (SNR)
av L
increases.

Some critical remarks on noise theory. The noise theory presented in this section is based
on the assumption that signal and noise at the reference input of the PLL are stationary. The
term stationary means the statistical parameters of signal and noise do not change with time—
that is, the power spectrum of noise always remains the same. In many applications of
communication, this condition is not met: the reference signal can almost disappear in some
time intervals due to fading, for example. When the input signal of a PLL gets momentarily
lost, performance of the PLL depends largely on the type of phase detector used. As we will
see, the loop filter also has some influence, though minor.
When comparing the four types of phase detectors discussed in this chapter, we note that the
multiplier and EXOR phase detectors are level-sensitive, whereas the JK-flipflop and PFD are
edge-sensitive. Assume the PLL uses the multiplier phase detector. If the input signal u fades
1
away, it becomes nearly zero, and only noise is left. Because that noise is uncorrelated with
the (down-scaled) output signal u ′ of the VCO (cf. Fig. 2.1), the average output signal
2
is zero. The situation is about the same when the EXOR is utilized. When the reference signal
u disappears, the signal at the reference input (after reshaping) hangs up at either a “low”
1
or a “high” level. Consequently, the output signal of the EXOR is either identical with the
down-scaled VCO output signal u ′ or with the logically inverted signal u ′. The average
2 2
value is zero again. What happens now with the output signal of the loop filter? The
situation is similar for the passive and the active lead-lag filter. With a zero input, the output is
also pulled toward zero with a time constant τ + τ for the passive, or with a time constant τ 1
1
2
for the active lead-lag filter. Hence, the frequency created by the VCO will relatively slowly
drift away toward the center frequency ω . When the reference signal disappears for an
0
extended period of time, the loop surely will get out of lock. If the active PI filter was used,
then the capacitor C (cf. Fig. 2.21a) has been charged to that voltage that was required to
1
create the appropriate VCO frequency before the reference input faded away. With zero input
signal, the voltage across capacitor C remains nearly unchanged, thus the instantaneous
1
output frequency of the VCO is held nearly constant. There is a good chance the loop is still in
lock when the reference signal reappears.
With edge-sensitive phase detector types, the situation is worse. In case of the JK-flipflop,
the phase detector output hangs up at a logic “low” level after the reference signal
disappears. Consequently, the output signal of the loop filter will be quickly pulled down to its
minimum level, and the VCO output frequency also runs away quickly. The same holds true
for the PFD. As soon as the reference signal fades away, the PFD will go into its −1 state
(output at logic “low”). Again the VCO output frequency will run away quickly.

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