Page 200 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL APPLICATIONS PART 1: INTEGER-N FREQUENCY
SYNTHESIZERS Ronald E. Best 123
■ N is always greater than or equal to N .
1 2
■ As shown by the AND gate in Fig. 6.4, underflow below 0 is inhibited in the case of the ÷
N counter. If this counter has counted down to 0, further counting pulses are inhibited.
2
The operation of the system shown in Fig. 6.4 becomes clearer if we assume that the ÷N
1
counter has just counted down to 0 and both counters have been loaded with their preset
values N and N , respectively. We now have to find the number of cycles the VCO must
2
1
produce until the same logic state is reached again. This number is the overall scaling factor
N of the arrangement shown in Fig. 6.4. As long as the ÷N counter has not yet counted
tot
2
down to 0, the prescaler is dividing by V + 1. Consequently, both the ÷N and the ÷N
1 2
counters will step down by one count when the VCO has generated V + 1 pulses. The ÷N 2
counter will therefore step down to 0 when the VCO has generated N · (V + 1) pulses. At
2
that moment, the ÷N counter has stepped down by N counts—that is, its content is N − N .
1
2
1
2
The scaling factor of the dual-modulus prescaler is now switched to the value V. The VCO
will have to generate additional (N − N )V pulses until the ÷N counter steps to 0. When the
1 2 1
content of N becomes 0, both the ÷N and the ÷N counters are reloaded to their preset
2
1
1
values, and the cycle is repeated.
How many pulses N did the VCO produce to run through one full cycle? N is given by
tot tot

Factoring out yields the simple expression

(6.2)

As stated earlier, N must always be greater than or equal to N . If this were not the case,
2
1
the ÷N counter would be stepped down to 0 earlier than the ÷N counter, and both counters
1
2
would then be reloaded to their preset values. The dual-modulus prescaler never would be
switched from V + 1 to V, so the system could not work in the intended way.
If V = 10, Eq. (6.2) becomes

(6.3)

In this expression, N represents the units and N the tens of the overall division ratio N .
2 1 tot
Then N must be in the range of 0–9, and N can assume any value greater than or equal to
2
1
9—that is, N = 9. The smallest realizable division ratio is therefore
1min

The synthesizer of Fig. 6.4 is thus able to generate all integer multiples of the reference