Page 202 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL APPLICATIONS PART 1: INTEGER-N FREQUENCY
SYNTHESIZERS Ronald E. Best 124
Other factors can of course be chosen for V. If V = 16, the dual-modulus prescaler would
divide by 16 or 17. The overall division ratio would then be

Now N would be required to have a range of 0 to 15, and the minimum value of N would
1
2
be N = 15. In this case, the smallest realizable division ratio N would be 240.
1min tot,min
Let us again assume that V is chosen at 10, and that the (scaled-down) reference frequency
f of the system in Fig. 6.4 is 10 kHz. The smallest output frequency would then be 90 · f =
1
1
900 kHz.
For the circuits inside the dashed enclosure, CMOS devices are normally used. The
counting frequency of older CMOS ICs (such as the old series 74Cxxx) has been limited to
approximately 3 MHz, so when using these devices a maximum frequency of only about 30
MHz could be realized for a prescaler ratio of V = 10. To extend the frequency range, larger
prescaler ratios, say V = 100, became desirable. Using V = 100, ratio N would be
tot

where N must now cover the range of 0 to 99, and N must be at least 99. It should be noted,
1
2
however, that now the lowest division ratio N is no longer 90 but has been increased to
tot,min

If the reference frequency f is still 10 kHz, the lowest frequency to be synthesized is now
1
99 MHz.

Four-modulus prescalers
Fortunately, there is another way, which extends the upper frequency range of a frequency
synthesizer but still allows the synthesis of lower frequencies. The solution is the four-
modulus prescaler (Fig. 6.5). The four-modulus prescaler is a logical extension of the dual-
modulus prescaler. It offers four different scaling factors, and two control signals are required
to select one of the four available scaling factors.
As an example, the four-modulus prescaler shown in Fig. 6.5 can divide by factors of 100,
101, 110, and 111. 11,36 By definition, it scales down by 100 when both control inputs are
LOW. The internal logic of the four-modulus prescaler is designed so that the scaling factor is
increased by 1 when one of the control signals is HIGH, or increased by 10 when the other
control signal is HIGH. If both control signals are HIGH, the scaling factor is increased by 1 +
10 = 11.
As seen in Fig. 6.5, there are no longer two programmable ÷N counters in the system, but
three: ÷N , ÷N , and ÷N dividers. The overall division ratio N tot of this arrangement is
1
3
2
given by