Page 272 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL APPLICATIONS PART 2: FRACTIONAL-N FREQUENCY
SYNTHESIZERS Ronald E. Best 161
frequency synthesizer; each reference cycle has a duration corresponding to 5.5 cycles of the
output signal u , which is shown in the second trace. The third trace represents the down-
2
scaled output signal u ′. In the first reference cycle shown, the down scaler divides by 6;
2
hence, 6 cycles of u correspond to one reference cycle. In the second reference cycle, the
2
down scaler divides by 5; hence, 5 cycles of u equal one reference cycle. We easily recognize
2
that in the first reference cycle the u ′ signal leads the u signal by a quarter of an output
2
1
cycle. In the second reference cycle, however, the u ′ signal lags u by a quarter of an output
2 1
cycle and so forth. The fourth trace shows the state of the output signal of the phase-frequency
detector (Q). In the first reference cycle, Q becomes −1 during a quarter of an output cycle—
that is, the phase error becomes negative. In the second reference cycle, Q is set to +1 during a
quarter of an output cycle, and the phase error becomes positive. Consequently, the phase
error θ oscillates between positive and negative values in consecutive reference cycles—that
e
is, the PFD output signal contains an AC component whose frequency is half the reference
frequency. This leads to a spur that is displaced by f /2 from the carrier frequency f . It is
ref 0
easily shown that for other fractional division ratios, the spurs will appear at other locations in
the frequency spectrum. For a division ratio of 5.2, for example, a spur will be displaced by
f /5 from the carrier. For a division ratio of 5.1, a spur will be displaced by f /10, and so on.
ref ref
Of course, these spurs must be suppressed as much as possible. In the past, analog techniques
have been used, as will be discussed in Sec. 7.2. These methods are considered obsolete today;
in the majority of modern synthesizer designs, digital methods dominate. They make use of
the so-called Sigma-Delta modulator (also known as the Delta-Sigma modulator). Digital
methods are preferred because they are much more easily implemented by integrated circuits
than the former analog ones. Digital spur reduction methods will be described in Sec. 7.3.
To obtain fractional divider ratios, we switched the preset count of down scalers from one
value to another—for example, from N to N + 1. Another technique will lead to the same
result: cycle steeling or pulse removal. When making use of cycle steeling, the down scaler of
the frequency synthesizer always counts down by the same divider ratio. Instead of switching
the preset count to N + 1 in some reference cycles, one output pulse (cf. the u signal in Fig.
2
7.1) is removed from the counting input of the down scaler in those cycles. This is equivalent
to down counting by N + 1 in the corresponding reference cycle. In Sec. 7.2, we will see an
example of cycle steeling.

Analog Spur Reduction Techniques

Figure 7.2 shows the block diagram of a fractional-N frequency synthesizer. Its division ratio
is the number N . F, where N is the integer part and F is the fractional part. For example, if a
division ratio of 26.47 is desired, then N = 26 and F = 0.47. The upper portion of Fig. 7.2,
separated by a dashed line, shows an ordinary frequency-synthesizer system generating an
output signal whose frequency is N times the reference frequency f . The block labeled
ref
“pulse-removing circuit”

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