Page 269 - Phase-Locked Loops Design, Simulation, and Applications
P. 269

Source : Phase-Locked Loops: Design, Simulation, and Applications, Sixth
                  Edition   Ronald E. Best                                                           159




                 Mixed-Signal PLL Applications Part 2:

                 Fractional-N Frequency Synthesizers




                 Realization of Fractional Divider Ratios

                 In the design example of Sec. 6.5, we realized a PLL frequency synthesizer capable of
                 creating output frequencies that are an integer multiple of the reference frequency (10
                 kHz). The synthesizer had a lock-in time of about 2 ms. This is not extremely fast.
                 Actually, there is an empirical relation between lock-in time T and reference frequency
                                                                              L
                 f , which says that the lock-in time T equals a number of reference periods, typically 10
                  ref
                                                      L
                 to 20 reference periods (a reference period has the duration 1/f ). 10,48  Where does that
                                                                               ref
                 range stem from?
                    In most practical PLL designs, the down-scaled center frequency ω ′ is much larger
                                                                                      0
                 than the natural frequency ω  of the PLL. Typically, ω ′ is about 20 times the natural
                                             n                          0
                 frequency. Note that in a PLL frequency synthesizer the down-scaled center frequency
                 ω ′ is identical with 2πf —in other words, the reference period equals one period of
                   0                       ref
                 down-scaled center frequency. Also remember that the lock-in time is approximately
                 equal to one period of natural frequency—that is







                 [cf. Eq. (3.62)]. Because the down-scaled center frequency is larger by a factor of 20 than
                 the natural frequency, the lock-in time corresponds to roughly 20 reference periods.
                    When the channel spacing of a frequency synthesizer must be narrow (for example, on
                 the order of 1 kHz), we are forced—at least in conventional synthesizer circuits—to
                 choose a low reference frequency. As we have seen, this results in a slow lock-in time. In
                 a conventional synthesizer (that is, in the type of synthesizer we considered hitherto) the
                 output frequency has always been an integer multiple of the reference frequency—for
                 example, 10 · f , 11 · f    ref,  12 · f , and so on. Assuming f ref  = 10 kHz, we could
                                                       ref
                                  ref
                 create frequencies of 100 kHz, 110 kHz,



                Printed from Digital Engineering Library @ McGraw-Hill (www.Digitalengineeringlibrary.com).
                Copyright ©2004 The McGraw-Hill Companies. All rights reserved.
                Any use is subject to the Terms of Use as given at the website.
   264   265   266   267   268   269   270   271   272   273   274