Page 306 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL APPLICATIONS PART 2: FRACTIONAL-N FREQUENCY
SYNTHESIZERS Ronald E. Best 180

Figure 7.16 An nth-order ΣΔ ADC with weighted feedforward and weighted feedback paths.

compensation. Here, the output signal of the one-bit DAC is not only fed to the input of the
first integrator but to all integrators using weights a through a .
1
n
Another way to obtain stable operation is to combine both feedforward and feedback paths,
as shown in Fig. 7.16. The signals fed back are scaled by weights a to a , whereas the fed
1 n
forward signals are scaled by weights b to b .
n
1
When one of these configuration has been chosen for the nth-order ΣΔ ADC, the scaling
factors a and/or b must be computed in order to obtain the required frequency response NTF
i
i
(z). Determination of scaling factors will be shown by the example of the feedforward
configuration in Fig. 7.14. We assume the designer has predifined a suitable NTF(z), by
selectying either a Butterworth or a Chebishev 2 highpass function. By using a digital filter
design program, the designer will have obtained the NTF(z) in the form

(7.23)

where the c and d are the filter coefficients determined by the filter design program. This
i
i
expression must now be equal with NTF (z), as given in Eq. (7.22), which is
FF

(7.24)

Because the coefficients of all the powers in z in the denominator must be the same on both
sides of the equation, this yields n equations to determine the a weights. (Note that the
i