Page 199 - Programming Microcontrollers in C

184 Chapter 4 Small 8-Bit Systems

To clear bits in the TSR, the program must first access the TSR
followed by an access of the LSB of the register associated with the bit
that must be reset in the TSR. This sequence can lead to problems in
dealing with the counter register. Suppose you are attempting to mea­
sure an elapsed time and are reading the counter register at random
times and you also will read the TSR to service timer requirements. It
is possible in these circumstances to accidentally reset the TOF bit
when it is undesired. To avoid this problem, an alternate counter regis­
ter has been designed into the M68HC05 devices. The alternate register
always contains the same values as the prime register, but the TOF bit
in the TSR is not reset when the alternate register is read.

Counter Register

The counter register is found in the memory locations 0x18 and
0x19. The least significant byte of the counter is in 0x19. An alter­
nate counter register is found in addresses 0x1a and 0x1b with 0x1b
being the least significant byte of this register. These registers are
clocked at the same time and are incremented from low values to
higher values. The counters are clocked at one-fourth of the internal
processor clock, which in turn is one-half the oscillator frequency.
The clocking frequency is one-eighth the crystal frequency, and the
clocking period is 2 microseconds when the crystal frequency is 4
MHz. These ratios are not adjustable in the M68HC05B6.
The free-running counter values can be read at any time. A read
sequence that reads only the least significant byte will receive the
count value at the time of the read. If the most significant byte of
either counter is read, the count value will be received and the con­
tents of the least significant byte will be transferred to a buffer. This
value will remain in the buffer until the program reads the contents
of the least significant byte of the register. The value received for this
read is the buffered value saved when the most significant byte was
read. The most significant byte, MSB, can be read several times prior
to reading the least significant byte, LSB, and the contents of the
buffer will remain unchanged. After the MSB has been read and the
LSB has been buffered, the free-running counter continues to be
incremented at its normal rate. If the MSB/LSB read sequence is
started, it is necessary to read the LSB to complete the sequence.
The counter is 16 bits, and when the register overflows from