Page 200 - Programming Microcontrollers in C

Timers 185

0xffff to 0x0000, the timer overflow (TOF) bit is set. This event can
cause an interrupt if the TOIE bit is set. Since the register is clocked
at 2 microseconds, the interval between TOF is 0.131072 seconds.

Input Capture Registers
There are two input capture registers called ICR1 and ICR2.
ICR1 is found at addresses 0x14 and 0x15, and ICR2 is located at
addresses 0x1c and 0x1d. The lower address always contains the MSB
of a 16-bit number. With the exception of the edge detection system
discussed in the TCR section, these two registers operate the same.
ICR1 can be set to respond to either a rising edge or a falling edge
on the timer compare input pin TCAP1. If IEDG1 is 0, ICR1 re­
sponds to a falling edge on TCAP1. Otherwise, if IEDG1 is 1, ICR1
responds to a rising edge on TCAP1. ICR2 responds only to a fall­
ing edge on TCAP2. An interrupt will also accompany an input capture
if the corresponding ICIE bit is set in the TCR.
The contents of the free-running counter are transferred to the
input capture registers each clock cycle. Therefore, the registers con­
tain a value that corresponds to the most recent input capture. After a
read of the most significant byte of the input capture register, the
transfer of new data to the least significant byte of the input capture
register is inhibited until this byte is read. At no time during this
sequence is the counter register inhibited.

Output Compare Registers

There are two output compare registers. OCR1 is found at ad­
dress locations 0x16 and 0x17 while OCR2 is located at 0x1e and
0x1f. Again the lower addresses contain the MSB of these 16-bit
numbers. These registers may be read or written at any time regard­
less of the timer hardware. If the output compare functions are not
utilized, these four bytes can be used for data storage. Their contents
are not altered at reset. There is only one output compare interrupt
bit that is used for both output compares in the system.
The contents of the output compare registers are compared with
the contents of the counter register each cycle of the counter register.
If a match is found with either output compare register, the corre­
sponding output compare flag—OCF1 or OCF2— bit is set. Also,
the value of proper output level bit—OLVL1 or OLVL2—is trans­