Page 344 - Satellite Communications, Fourth Edition

324 Chapter Eleven

where P P , and so on are the parity symbols selected by the encoding
2
1
rules from the symbol alphabet A, B, C, and D. This process is illustrated
in Fig. 11.1.
At the decoder, these are the only words that are recognized as being
legitimate and can be decoded. The other possible codewords not formed
by the rules but which may be formed by transmission errors will be
detected as errors and corrected. It will be observed that a codeword con-
sists of 6 bits, and one or more of these in error will result in a symbol
error. The R-S code is capable of correcting this symbol error, which in
this simple illustration means that a burst of up to 6 bit errors can be
corrected.
R-S codes do not provide efficient error correction where the errors are
randomly distributed as distinct from occurring in bursts (Taub and
Schilling, 1986). To deal with this situation, codes may be joined together
or concatenated, one providing for random error correction and one for
burst error correction. Concatenated codes are described in Sec. 11.6. It
should be noted that although the encoder and decoder in R-S codes oper-
ate at the symbol level, the signal may be transmitted as a bit stream,
but it is also suitable for transmission with multilevel modulation, the
levels being determined by the symbols. The code rate is r K/N,and
c
the code is denoted by (N, K). In practice, it is often the case that the
8
symbols are bytes consisting of 8 bits; then q 2 256, and N q
1 255. With t 8, a NASA-standard (255, 239) R-S code results.
Shortened R-S codes employ values N N l and K K l and
are denoted as (N , K ). For example, DirecTV (see Chap. 16) utilizes a
shortened R-S code for which l 109, and digital video broadcast (DVB)
utilizes one for which l 51 (Mead, 2000). These codes are designed to
correct up to t 8 symbol errors.

11.4 Convolution Codes
Convolution codes are also linear codes. A convolution encoder consists
of a shift register which provides temporary storage and a shifting oper-
ation for the input bits and exclusive-OR logic circuits which generate
the coded output from the bits currently held in the shift register.
In general, k data bits may be shifted into the register at once, and n
code bits generated. In practice, it is often the case that k 1 and n 2,
giving rise to a rate 1/2 code. A rate 1/2 encoder is illustrated in Fig. 11.2,
and this will be used to explain the encoding operation.
Initially, the shift register holds all binary 0s. The input data bits are
fed in continuously at a bit rate R , and the shift register is clocked at
b
this rate. As the input moves through the register, the rightmost bit is
shifted out so that there are always 3 bits held in the register. At the end
of the message, three binary 0s are attached, to return the shift register