Page 348 - Satellite Communications, Fourth Edition
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328  Chapter Eleven


                               The CDV-10MIC is a single integrated circuit which implements all the functions
                               required for a constraint length 7, rate 1/2, and punctured 2/3 or 3/4 rate, convolu-
                               tional encoder, and Viterbi algorithm decoder. Important features of this chip are:
                                 Full decoder and encoder implementation for rates 1/2, 2/3, and 3/4
                                 Complies with INTELSAT IESS-308 and IESS-309 specifications
                                 Extremely low implementation margin
                                 No external components required for punctured code implementation
                                 Operates at all information rates up to 10 Mbits/s. Higher speed versions are
                                 under development
                                 All synchronization circuits are included on chip. External connection of ambi-
                                 guity state counter and ambiguity resolution inputs allows maximum application
                                 flexibility
                                 Advanced synchronization detectors enable very rapid synchronization. Rate, 3/4
                                 block and phase synchronization in less than 8200 information bits (5500 trans-
                                 mitted symbols).
                                 Soft decision decoder inputs (3 bits, 8 levels)
                                 Erasure inputs for implementing punctured codes at other rates
                                 Path memory length options to optimize performance when implementing high-
                                 rate punctured codes
                                 Error-monitoring facilities included on chip
                                 Synchronization detector outputs and control inputs to enable efficient synchro-
                                 nization in higher-speed multiplexed structures.

                              Figure 11.4 Specifications for a single-chip Viterbi codec. (Courtesy of Signal Processors,
                              Ltd., Cambridge U.K.)



                                Decoding is a more difficult problem than encoding, and as the exam-
                              ple suggests, the search process could quickly become impracticable for
                              long messages. The Viterbi algorithm is used widely in practice for
                              decoding. An example of a commercially available codec is the CDV-
                              10MIC single-chip codec made by Signal Processors Limited, Cambridge,
                              U.K. The data sheet for this codec is shown in Fig. 11.4. The CDV-10MIC
                              utilizes Viterbi decoding. It has a constraint length of 7 and can be
                              adjusted for code rates of 1/2, 2/3, and 3/4 by means of what is termed
                              punctured coding. With punctured coding, the basic code is generated
                              at code rate 1/2, but by selectively discarding some of the output bits,
                              other rates can be achieved (Mead, 2000). The advantage is that a single
                              encoder can be used for different rates.



                              11.5 Interleaving
                              The idea behind interleaving is to change the order in which the bits
                              are encoded so that a burst of errors gets dispersed across a number
                              of codewords rather than being concentrated in one codeword.
                              Interleaving as applied in block codes will be used here to illustrate
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