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                                                INSPECTION, MEASUREMENT, AND TEST

                                                                        INSPECTION, MEASUREMENT, AND TEST  19.31

                                  number of frequency hops per second. The amount of noise present on the system is always a con-
                                  sideration. RF, because of the frequency involved, has special fixturing considerations, not only for
                                  the DUT board, but also for the construction and location of system resources. Also with today’s
                                  COT pressures, the architecture needs to support multisite configurations both in performance and
                                  resource availability as mentioned in this section.

                                  Basic RF SOC Test Setups.  The basic test setup for an RF SOC is similar to mixed-signal testing.
                                  Briefly, this includes bringing any EDA data into the test environment and consulting with the spec-
                                  ification sheet for the test list and basic setup conditions, including stimulus signal and where and
                                  when to measure outputs. The parameters that are measured could include traditional tests such as
                                  gain, linearity, and distortion tests or tests very specific to its RF functionality, which could include
                                  the system-level tests explained previously.

                      19.2.9 System-Level Integration
                                  Today higher integration and lower cost requirements are driving some markets toward system-level
                                  integration.  The consumer market typically drives smaller application form factors and cheaper
                                  prices; some examples of this are—cell phones, CD and DVD players, and PDAs.
                                    An SOC refers to the complexity level where any of the previously mentioned tests and IC
                                  disciplines can be included, such that the entire system is included on a single chip. This has
                                  many COT and performance benefits. Typically, the functions for these are stand-alone IP blocks
                                  that can be readily glued into designs that are on the same die, enabling complex SOC designs to
                                  be completed rapidly. These could also come complete with test vectors and a program as will be
                                  discussed later.
                                    A system-in-a-package (SiP) is a device that combines multiple individual semiconductor die into
                                  a single package. The partitioning of the functions of the different die is determined by optimizing
                                  technologies to achieve the end result—improved performance, minimizing cost, improving TTM,
                                  or a combination of these.
                                    There are many test ramifications of system-level testing, including increased functional and per-
                                  formance complexities, increased pin (package) and pad (wafer die) counts, faster time-to-market,
                                  and even the potential to require multiple pass testing because one tester may not have all the nec-
                                  essary functionality. This trend has driven test vendors who wish to test SOCs and SiPs to integrate
                                  all these technologies into a single platform from single “niche” market tester backgrounds. Multiple
                                  pass testing with single technology niche testers is not usually economically feasible, especially in
                                  the consumer marketplace. An exception to this, where multiinsertion testing can be more econom-
                                  ical than single-insertion testing, is in cases where resource utilization is grossly mismatched. For
                                  example, if a large DRAM is one of the die in the package, it may be more economical to test this
                                  in a separate insertion on a lower-cost memory tester. Another good solution to this requirement
                                  would be to resort to a KGD strategy that did not require full memory testing in the SIP package.
                                  The SOC tester of today incorporates architecture from all the market segments outlined in this sec-
                                  tion, although digital, mixed signal, memory and RF are the dominant features. With this increase in
                                  capability, there needs to be a focus on COT, because of consumer market demands. Test vendors are
                                  responding with more parallelism to meet these needs. They are also working on ways to speed up
                                  TTM including concurrent engineering, automatic development, and test emulation, all of which will
                                  be explored in Sec. 19.5.



                      19.3 HOW TO PREPARE, PLAN, SPECIFY, SELECT VENDOR,
                      AND PURCHASE TEST EQUIPMENT

                                  This section will discuss a methodical approach of how to prepare, plan, specify, select vendor, and
                                  purchase test equipment. Some of these steps may be skipped for a variety of reasons, such as time,
                                  cost, and available resources. Also purchase decisions may not be made only on new technologies or

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