Page 145 - Troubleshooting Analog Circuits

I32 IO. The Analog/Digital Boundary

jump, or “glitch.” Although you can build such a circuit, it’s a lot more difficult than
building a more conventional S/H circuit. You usually find glitch-free S/H circuits
only in “deglitchers,” which are more expensive than most S/H circuits. Several
module and hybrid manufacturers provide this kind of precision device. Even though
it doesn’t settle out instantly, a deglitcher is fast and consistent in its settling.
However, it still does take some time to settle within 5 mV.

Aperture Time Still Causes Confusion
There’s one area of specsmanship where the S/H circuit is clouded in confusion.
That area is the aperture-delay specification. (Maybe someday I’ll write a data sheet
and drive away the cloud. Ask me for a data sheet on the LF6197.. . . ) One technique
for measuring and defining aperture delay is to maintain Vi, at a constant level and
issue the HOLD command. If after a short delay, Vi, jumps by a few volts, the
smallest spacing between the HOLD command and the Vi, jump that causes no false
movement of V,,, is one possible definition of the tmERmRE DELAY.
Another way of defining and measuring aperture delay is to let Vi, move smoothly
at a well-defined rate. Shortly after you issue the command to switch the circuit to the
HOLD mode, V,,, stops changing. The value at which V,,, stops corresponds to the
value of Vi, at a particular point in time. You can define the aperture delay as the
difference between this point and the time at which the mode-control signal crossed
the logic threshold. The uncertainty in the value of the aperture delay is then the
aperture uncertainty. Depending on how the circuit was optimized, that delay can be
positive or negative or practically zero-perhaps only 1 ns or less. Now, will the real
definition of aperture time please stand up?
I think that both of the characteristics I have described are of interest to people at
different times. But, how can you avoid the problem of a person expecting one of
these characteristics and actually getting the other? I invite your comments on who
wants to buy which characteristic, and where to find a definition. I’ve looked in mili-
tary specs and at many data sheets, and the issue still seems pretty unclear.
Another instance in which a S/H circuit can have trouble is when its output is con-
nected to a multiplexer, for example, when multiple S/H circuits drive a single ADC
to achieve simultaneous sampling of many channels of dynamic analog data. If the
multiplexer, which had been at a voltage of, say, +10 V, suddenly connects to the
output of a S/H circuit whose output is at -10 V, the circuit’s output will twitch and
then may jump to a false level because the multiplexer will couple a little charge
through the S/H circuit into the hold capacitor. The industry-standard LF398 is fairly
good at driving multiplexers, but if you get a big enough capacitance on the multi-
plexer output-perhaps 75 pF-and it’s charged to a voltage more than 10 V away
from the S/H circuit’s output voltage, even the LF398’s output can jump. I don’t have
a real solution for this problem, but if you are aware that it can happen, at least you
won’t tear out all your hair trying to guess the cause. You will recognize the problem,
and then tear out your hair. About all you can do is try to minimize the capacitance
on the output of the multiplexer. One way to do this is by using a hierarchical con-
nection of submultiplexers.

Not Much Agreement on Acquisition-Time Definition
Another area of S/H-circuit confusion is acquisition time. I have seen at least one
data sheet that defined acquisition time as the time required to go from HOLD to
SAMPLE and for the output to then settle to a value corresponding to a new value of