Page 141 - Troubleshooting Analog Circuits

I28 IO. The Analog/Digital Boundary

specify this parameter, because some DACs are good and some aren’t. I even recall a
case where I had to preload the TTL outputs of a modular DAC’s internal storage
register with a 2 kR resistor from each line to ground. Otherwise they would over-
shoot when going HIGH and then recover with a long slow tail, an attenuated version
of which would then appear on the DAC output.
On-chip buffers at a DAC’s input can help cut down feedthrough from the bit lines
to the analog output, but will not completely eliminate it. The bus can move around
incessantly, and capacitive coupling or even PC-board leakage will sometimes cause
significant crosstalk into the analog world. Even IC sockets can contribute to this
noise. If you could prove that such noise wouldn’t bother your circuit, you could for-
get about it. The problem is that you can only make meaningful measurements of such
effects on an operating prototype+omputer modeling isn’t going to simulate this.
Multiplying DACs are popular and quite versatile. However, a multiplying DAC’s
linearity can be degraded if the output amplifier’s offset voltage isn’t very close to
zero. I’ve heard this degradation of linearity estimated at 0.01% per millivolt of
offset. Fortunately, low-offset op amps are pretty cheap these days. At least a low-
offset op amp is cheaper than a trim-pot.
Another imperfection of any multiplying DAC is its AC response for different
codes. If you put in a 30-kHz sine wave as the reference, you shouldn’t really be
surprised if the gain from the reference to the output changes by more than 1 LSB
when you go from a code of lo00 oo00 to a code of 01 11 1 1 11. In fact, if the fre-
quency is above 5 kHz, you may find a 0.2% or larger error because the multiplying
DAC’s ladders, whose attenuation is a linear function of the input code at DC, be-
come slightly nonlinear at high frequencies due to stray capacitance. The non-
linearity can be 0.2%, and the phase change as you vary the input code can exceed
2O, even with a 5-kHz reference. So don’t let these AC errors in multiplying DACs
surprise you.
Another problem with DACs is the output glitch they can produce when going
from one code to an adjacent one. For example, if a DAC’s input code goes from
lo00 0000 to 01 11 11 11 and the delay for the rising bits is much different from that
for the falling bits, the DAC output will momentarily try to go to positive or negative
full scale before it goes to a value corresponding to the correct code. Though well-
known, this problem is a specialized one. One possible solution calls for precisely
synchronous timing. Multiple fast storage registers can also help to save the day. But
if the best synchronous timing is not good enough, a deglitcher may be the solution.

ADCs Can Be Tough and Temperamental

Like DACs, many A/D converters (ADCs) do exactly what they are supposed to, so
what can go wrong? Most problems involve a characteristic that is mentioned on too
few data sheets: Noise. When an analog signal moves slowly from one level to an-
other, it would be nice if the ADC put out only the code for the first voltage and then,
at the appropriate threshold, began to produce only the code for the other voltage. In
practice, there is a gray area where noise causes codes to come up when they
shouldn’t. On a good ADC, the noise can often be as low as 0.1 or 0.05 LSB p-p. But
when you come to a worst-case condition (which with successive-approximation
converters often occurs at or near a major carry-for example, where the output
changes from 1 OOO oo00 to 01 1 1 1 11 11, the noise often gets worse, sometimes
climbing to 0.5 LSB p-p or more. I wouldn’t want to buy an ADC without knowing
how quiet it was. I’d have to measure the noise myself, as shown in Figure 10.7,
because virtually nobody specifies it. That’s not to say all ADCs are bad, just that