Page 304 - ARM 64 Bit Assembly Language
P. 304

CHAPTER 9

                     Floating point




                     For ARMv7 and previous architectures, floating point is provided by an optional Vector Float-
                     ing Point (VFP) coprocessor. Many ARMv7 processors also support the NEON extensions.
                     All AArch64 processors support a version of NEON referred to as Advanced SIMD. For
                     brevity, this book will often use the term NEON to refer to Advanced SIMD. Advanced SIMD
                     supports not only floating point, but also integer and fixed point operations. The remainder of
                     this chapter will cover the floating point operations that are inherited from, or similar to, the
                     instructions provided by the older VFP coprocessor.


                     9.1 Floating point overview


                     Historically, ARM has implemented floating point operations by adding a coprocessor to the
                     CPU. The coprocessor extends the instruction set that is supported by the system. There are
                     five major revisions of the ARM floating point instruction set and coprocessor:
                     VFPv1: Vector Floating Point coprocessor version 1 is obsolete.
                     VFPv2: An optional extension to the ARMv5 and ARMv6 processors. VFPv2 has 16 64-bit
                           FPU registers.
                     VFPv3: An optional extension to the ARMv7 processors. It is backwards compatible with
                           VFPv2, except that it cannot trap floating-point exceptions. VFPv3-D32 has 32 64-bit
                           FPU registers. Some processors have VFPv3-D16, which supports only 16 64-bit FPU
                           registers. VFPv3 adds several new instructions to the VFP instruction set.
                     VFPv4: Implemented on some Cortex ARMv7 processors. VFPv4 has 32 64-bit FPU regis-
                           ters. It adds both half-precision extensions and multiply-accumulate instructions to the
                           features of VFPv3. Some processors have VFPv4-D16, which supports only 16 64-bit
                           FPU registers.
                     NEON: Defines Single Instruction Multiple Data (SIMD) extensions to the instruction set.
                           NEON supports the floating point instruction set along with integer operations. The
                           NEON instruction set allows for a single instruction to perform operations on multiple
                           pieces of data.
                     AArch64 integrates floating point and SIMD more tightly into the processor core, while still
                     maintaining instructions that are similar to the original FP/NEON instruction set.


                     ARM 64-Bit Assembly Language
                     https://doi.org/10.1016/B978-0-12-819221-4.00016-X  293
                     Copyright © 2020 Elsevier Inc. All rights reserved.
   299   300   301   302   303   304   305   306   307   308   309